Emitter function logic latch and counter circuits

Details Emitter function logic latch and counter circuits Emitter function logic latch and counter circuits

1980-09-29

1983-03-29

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307272A, 307455, 377 64, 377116, H03K 328, H03K 3289

Patent

active

043785050

ABSTRACT:
An EFL D-type latch employing an EFL storage cell (17) controlled by a two-level tree of differential transistor pairs (12, 14 and 32, 34). Also described are counter cells, up counters, down counters and up/down counters, including binary, hexadecimal and BCD types, which can be formed from master/slave combinations of D-type and D-type latches. Examples of specific three-level and four-level EFL realizations of the counter cells are also described.

REFERENCES:
patent: 3040192 (1962-06-01), Slobodzinski
patent: 3795822 (1974-03-01), Skokan
patent: 4041326 (1977-08-01), Robinson
patent: 4145623 (1979-03-01), Doucette
patent: 4214173 (1980-07-01), Popper
M. Cooperman, "High Speed Current Mode Logic for LSI" IEEE Transactions on Circuits and Systems, vol. CAS-27, No. 7, pp. 626-635, Jul. 1980.
Z. E. Skokan, "Emitter Function Logic-Logic Family for LSI" IEEE Journal of Solid-State Circuits, vol. SC-8, No. 5, pp. 356-361, Oct. 1973.
M. I. Elmasry et al., "Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers", IEEE Transactions on Computers, vol. C-24, No. 3, pp. 250-258, Mar. 1975.
J. Kane, "A Low-Power, Bipolar, Two's Complement Serial Pipeline Multiplier Chip", IEEE Journal of Solid-State Circuits vol. SC-11, No. 5, pp. 669-678, Oct. 1976.
W. Braeckelmann et al., "A Masterslice LSI for Subnanosecond Random Logic", IEEE Journal of Solid-State Circuits vol. SC-14, No. 5, pp. 829-832, Oct. 1979.

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