Emitter coupled semiconductor memory device having a low potenti

Static information storage and retrieval – Interconnection arrangements – Transistors or diodes

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365226, 365227, G11C 506, G11C 1134

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047409185

ABSTRACT:
A semiconductor memory device which includes a high potential source, a low potential source, and a word line driver portion which makes the potential of selected word lines a selection level lower by a predetermined potential than the high potential source. Memory cells are connected to the word lines. A first low potential source or a second potential source is connected to the low potential source. A plurality of transistors are provided in the word line driver portion so as to connect a plurality of stages. When the memory has a sufficient power source margin, the word line driver is formed as a two-stage device so as enable high speed operation. When the memory has an unsufficient power source margin, the word line driver is formed as a one-stage device so as to ensure a sufficient power source margin.

REFERENCES:
patent: 3365707 (1968-01-01), Mayhew
patent: 3898630 (1975-08-01), Hansen et al.
patent: 4347588 (1982-08-01), Hoffmann et al.
patent: 4394657 (1983-07-01), Isogai et al.
patent: 4586169 (1986-04-01), Itoh et al.
patent: 4627034 (1986-12-01), Herndon

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