Emitter coupled multiplier array

Details Emitter coupled multiplier array Emitter coupled multiplier array

1977-04-04

1978-10-24

Malzahn, David H.

Boots, shoes, and leggings

364760, G06F 750, G06F 752

Patent

active

041225279

ABSTRACT:
A high speed multiplier array implemented with a current switch emitter follower logic gate employs an inverted carry signal internal to the array. External carry signals received by the array are first inverted for internal processing. This implementation eliminates the necessity of employing a buffer gate between subarray integrated circuit chips or cells and thus decreases propagation delays in the overall array.

REFERENCES:
patent: 3249746 (1966-05-01), Helbig et al.
patent: 3465133 (1969-09-01), Booher
patent: 3932734 (1976-01-01), Parsons
C. W. Weller, "A High-Speed Carry Ckt. for Binary Adders", IEEE Trans. on Computers, vol. C-18, No. 8, Aug. 1969, pp. 728-732.

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