Emitter coupled logic latch with boolean logic input gating netw

Details Emitter coupled logic latch with boolean logic input gating netw Emitter coupled logic latch with boolean logic input gating netw

1987-10-30

1988-06-28

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307467, 307530, H03K 19086, H03F 345

Patent

active

047541733

ABSTRACT:
A latch circuit including an input logic network that incorporates emitter-coupled logic switching arrangements connected in multiple levels to perform logical operations on the received input signals. The latch circuit is controlled by differential clock signals coupled to a differential switch circuit that is connected to the input logic network to form another switch level. An output buffer is connected to the input logic network to generate output signals of selected logic voltage levels. When the differential clock signals are in a pass condition, the input logic network is enabled to transmit an output signal to the output buffer. When the differential clock signals are in a latch, or hold, condition, the input logic network is disabled and a feedback network is enabled to maintain the signal to the output buffer in the conditions it was in when the differential clock signals changed conditions.

REFERENCES:
patent: 3446989 (1969-05-01), Allen et al.
patent: 3906212 (1975-09-01), Poquntke
patent: 4145623 (1979-03-01), Doucette
patent: 4580066 (1986-04-01), Berndt

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