Emitter coupled logic latch circuit

Details Emitter coupled logic latch circuit Emitter coupled logic latch circuit

1989-06-30

1990-11-13

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072722, 365154, H03K 3288

Patent

active

049704176

ABSTRACT:
An ECL latch circuit comprises a data input part and a latch part. The data input part includes input transistors coupled in parallel and having bases for respectively receiving an input data and a clock signal, and an output transistor applied with a reference voltage. The data input part samples the input data responsive to the clock signal and outputs a level shifted data signal from a collector of the output transistor. The latch part includes a transistor which has a base for receiving the same clock signal, an emitter coupled transistor pair having bases respectively applied with the reference signal and an output signal of the ECL latch circuit, and a transistor having a base coupled to the collector of the output transistor and an emitter coupled to the base of the latter of the transistor pair.

REFERENCES:
patent: 4513283 (1985-04-01), Leininger
patent: 4626706 (1986-12-01), Allen et al.
patent: 4628217 (1986-12-01), Berndt
patent: 4810908 (1989-03-01), Suzuki et al.
patent: 4891531 (1990-01-01), Kobayashi et al.

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