Emitter coupled logic circuit with reduced power consumption and

Details Emitter coupled logic circuit with reduced power consumption and Emitter coupled logic circuit with reduced power consumption and

1991-07-01

1993-01-05

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072963, 307270, H03K 19086, H03K 1920

Patent

active

051773791

ABSTRACT:
An emitter coupled logic circuit includes a differential amplifier circuit provided between a higher potential source and a first lower potential source; an emitter follower first transistor whose base is connected to a first output node of the differential amplifier, whose collector is connected to the higher potential source, and whose emitter is connected to an output node; a second transistor whose collector is connected to the higher potential source, whose emitter is connecrted to a second lower potential having its potential higher than that of the first lower potential and whose base is connected to its collector through a resistor; and a pull-down third transistor whose collector is connected to the output terminal and whose emitter is connected to the collector of the second transistor through a resistor. The circuit may further include a capacitor which is connected between the second output node of the differential amplifier and the base of said third transistor. The power consumption of the circuit is reduced and the operation speeds thereof are improved.

REFERENCES:
patent: 4490630 (1984-12-01), Freeman
patent: 4906869 (1990-03-01), Masuoka
patent: 5012128 (1991-04-01), Chan
patent: 5041743 (1991-08-01), Matsumoto
patent: 5089724 (1992-02-01), Chuang et al.

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