Emitter coupled logic circuit with active pull-down

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307446, 307455, 307475, 364708, 365 63, H03K 19086, H03K 19092

Patent

active

043474462

ABSTRACT:
An emitter coupled logic gate incorporating an active pull-down transistor in the pull-down circuit with bias connections for the pull-down transistor including components in the differential input circuit of the gate so that the pull-down transistor is active only during a HIGH-to-LOW transition of the output logic signal. Single and plural input gates are described together with advantageous exemplary embodiments of integrated circuits utilizing active pull-down ECL gates formed on an IC chip to enable large signal fan-out to other circuits formed on the same IC chip or to off-chip utilization circuits.

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Chang et al., "Complementary Driver for Emitter-Coupled-Logic Gates"; IBM Tech. Discl. Bull.; vol. 19, No. 12, pp. 4614-4615; 5/7.
"Monolithic ECL 3-Input Gate Circuit; " MECL ICS Motorola Semiconductor Products Inc. (pub) 8/1963.

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