Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With enlarged emitter area
Reexamination Certificate
1999-11-29
2002-08-20
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
With enlarged emitter area
C257S144000, C257S164000, C257S341000, C257S348000, C257S409000, C257S580000, C257S581000, C257S582000, C257S583000, C257S584000, C257S572000, C257S577000
Reexamination Certificate
active
06437419
ABSTRACT:
BACKGROUND OF THE INVENTION
Using emitter ballasting resistors in insulated gate bipolar transistors (IGBTs) improves immunity to latch-up and improves short circuit ruggedness. Others have thought that the improvement is due to an increase in the voltage drop in the P-region beneath the N+source needed to activate a parasitic thyristor, and to de-biasing of the gate by the voltage drop in the ballast resistor. However, we have discovered a novel way for manufacturing devices where the ballast resistor is combined with the body effect of the device so that the voltage drop has negligible effect at operating current and adjusts the threshold voltage such that it increases by several volts under short circuit current conditions.
BRIEF SUMMARY OF THE INVENTION
In a semiconductor device such as an IGBT or other power devices such as DMOS, MOSFETs, and MCTs, the emitter is provided with an emitter ballast resistor and the body effect is modified by controlling the value of the emitter ballast resistor. The invention provides a method for more precisely controlling the size and resistance of ballast resistors without the use of a masking layer. The invention provides a source/emitter ballast resistor that is self-aligned with a sidewall spacer of the cellular gate structures.
The invention provides a semiconductor device with an integral source/emitter ballast resistor. The device is fabricated in a semiconductor substrate, typically an N-type substrate. The substrate has an elongated P-well region where the edges of the P-well form PN junctions with the N-type substrate at the surface. A single gate has a plurality of partial gate structures that are spaced apart from each other on the surface of the substrate. Each gate structure has a gate oxide or a gate insulator layer on the substrate surface with a conductive gate on top of the gate insulator. Two opposing gate structures cover opposite elongated ends of a P-well region. On the edges of the gate structures facing each other, each gate structure has a sidewall spacer insulator. Beneath the sidewall spacer insulator is a self-aligned, lightly doped N-type region that forms the emitter/source ballast resistor. Extending transverse to the opposing elongated emitter ballast resistors are one or more heavily doped N-type contact regions. The remaining surface of the substrate is doped with a P+ type dopant in order to eliminate the effect of the lightly doped N-type region, except for the region beneath the sidewall spacer insulators.
We found that under normal operation the threshold voltage of devices made with the invention increase by negligible amount, i.e., a few millivolts. However, when the device enters a short circuit operation, the emitter ballast resistors have a dramatic effect upon limiting the short circuit current. During short circuit operation, the body effect due to the emitter ballast resistor produces a threshold voltage that is anywhere from 2-4 volts greater than the normal threshold voltage. As such, a device under short circuit conditions will saturate sooner and therefore will be protected against carrying excess current.
The inventive process also includes a method for fabricating the novel structure. With this method, the elongated P-well is formed in the surface of the semiconductor with an N-type doping. The gate structure is formed on the surface of the semiconductor substrate. Then the P-well dopant is implanted into the surface of the substrate without need for a further mask. Next, again using the gate structure as a mask, an N-type dopant is implanted into the surface of the semiconductor. The N-type dopant is then diffused down into the semiconductor but remains substantially aligned with the edges of the gate structure. Next, the gate is modified to add a sidewall spacer. Sidewall spacing is a conventional step in gate fabrication. Next, the substrate is masked to establish N+ contact regions. This mask is a non-critical mask since the N-type contact regions will self-align with the emitter ballast resistors. Thereafter, the mask is stripped and the surface is again implanted with a P-type dopant in order to eliminate the effect of the lightly doped N-region. As such, the surface of the semiconductor provides alternate regions of P+ and N+. The N+ regions extend across the face of the semiconductor from one sidewall to the next. The edges of the N+ regions are connected to the emitter ballast resistors that extend along the length of the P-well beneath the sidewall spacers.
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B. Jayant Baliga, “Power MOS—BIPOLAR Devices”,Krieger Publishing Company, Malabar, Florida, pp 344-380.
Bhalla Anup
Muraleedharan Shenoy Praveen
Fairchild Semiconductor Corporation
Jaeckle Flieschmann & Mugel, LLP
Lee Eddie
Ortiz Edgardo
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