Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2007-09-11
2007-09-11
Shalwala, Bipin (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S036000, C345S076000, C345S098000, C345S204000, C315S169300, C340S870030
Reexamination Certificate
active
10693995
ABSTRACT:
An emissive display having pixels delimited by a plurality of scan lines and a plurality of signal lines intersecting with each other. Each pixel includes a memory circuit having at least a first inverter circuit including an electroluminescent device and including a display control circuit connecting in series a main circuit of at least one first transistor. The memory circuit stores display information of the pixel according to a conduction state or a non-conduction state of the main circuit of the first inverter, and controls an on state and an off state of the electroluminescent device.
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SID 99 Technical Digest, pp. 372-375.
Kaneko Yoshiyuki
Mikami Yoshiro
Ouchi Takayuki
Sato Toshihiro
Antonelli, Terry Stout and Kraus, LLP.
Hitachi , Ltd.
Kovalick Vincent E.
Shalwala Bipin
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