Embedding parasitic model for pi-fet layouts

Details Embedding parasitic model for pi-fet layouts Embedding parasitic model for pi-fet layouts

2001-04-23

2003-01-07

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Mesa formation

Reexamination Certificate

active

06503774

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for modeling a semiconductor device and more particularly to a method for modeling a Pi-FET by embedding equivalent circuit models for a single-fingered device all within capacitive, inductive and resistive parasitic elements associated with the semiconductor device, interconnects and the inter-relationships therebetween.
2. Description of the Prior Art
The capability to accurately forecast product yield of semiconductor devices, such as microwave monolithic integrated circuits (MMIC), is an invaluable asset in manufacturing. Yield forecasting allows for better allocation of limited manufacturing resources; identification of yield problems; and reduced manufacturing costs. In GaAs MMIC manufacturing, the drive to new markets under reduced design costs and reduced time-to-market cycles have increased the probability for RF yield problems. These risks become even more acute when RF performance specifications are pushed to the limits of the process in accordance with the current trend in an ever more competitive environment.
Addressing the cause of poor MMIC yield can be an insidious problem in that it may not be specific. In particular, RF yield problems may occur as a result of unrealized shortcomings distributed across the entire manufacturing process. The principle mechanisms which contribute to yield loss in an MMIC manufacturing process are illustrated in FIG.
1
. As shown, four out of seven possible mechanisms relate strongly to RF yield loss. Factors, such as unrealistic performance specification; poor design-for-manufacturing; and process variability may individually or accumulatively reduce the RF yield, thus raising the long term manufacturing costs as well as the design to manufacturing cycle time.
Various methods are used for RF yield forecasting. For example, both statistical and empirical modeling methods are known. Statistical modeling employs device models and circuit simulation while empirical modeling uses measured data. Such statistical models include Monte Carlo statistical models, correlated statistical models, boundary models and database models. Monte Carlo statistical models allow device model parameters to vary independently of each other by Gausian statistics while correlated statistical models are known to represent more realistic statistics in which the variations are constrained with correlation between the model parameters. Long-term model databases are typically created for the purpose of process control monitoring but can also be used in yield forecasting, for example, as disclosed in “A Product Engineering Exercise in 6-Sigma Manufacturability: Redesign of pHEMT Wideband LNA, by M. King et al., 1999
GaAs MANTECH Technical Digest,
pp. 91-94, April 1999.
Boundary models are a set of models that represent the “process corner performance”. Boundary models are known to be ideal for quickly evaluating the robustness of a new design to an anticipated process variation. Some manufacturers are known to develop methods that directly evaluate robustness through “process corner experimentation”, for example as disclosed “GaAs Fabs Approach to Design-for-Manufacturability”, by R. Garcia, et al. 1999
GaAs MANTECH Technical Digest,
pp. 99-102, April 1999. However, the boundary methods cannot be used to determine RF performance distributions that are fundamental to yield calculation. As such, this method is unsuitable for RF yield prediction.
Long-term model databases are a powerful tool for MMIC process control monitoring and typically consist of large samples of small signal equivalent circuit model extractions for single consistent device structures, measured under a standard set of bias conditions. Database models unambiguously capture true process variations through uniform sampling. Unfortunately, such models are limited to applications based closely around original measurements. For example, accurately extending a database model to represent a device with different bias conditions and layouts is problematic. Such determinations are labor intensive, as generally set forth in; “A Product Engineering Exercise in 6-Sigma Manufacturability: Redesign of a pHEMT Wide-Band LNA,” supra. In other circumstances, it is virtually impossible or unadvisable to apply database results, for example, to predict low noise or low signal results from a small signal model.
Monte Carlo statistics are simple to implement for RF yield simulations. However, forecasts produced by this method are relatively inaccurate and are normally used for worse case yield analysis. In particular, examples of inaccurate yield forecasts provided by Monte Carlo and correlated statistical models are shown in
FIGS. 2A and 2B
, which illustrate simulated versus actual noise and gain statistics for a 22-26 GHz GaAs pHEMT LNA. As illustrated, the squares and circles represent simulated data points by correlated statistical and Monte Carlo statistical models, respectively and the dashed line represents the measured data points.
Correlated statistical models provide a better method yet inaccurate correlated statistic models provide a better method, however, the results from this method can also be inaccurate. Another drawback of correlated statistical models is that substantial model databases are also needed in order derive the correlation which subject method to restrictions that normally plague long-term model databases.
As mentioned above, empirical forecasting is known to be used for forecasting RF yield. In such empirical forecasting methods, the long-term RF yield of one circuit is predicted by known process dependent RF yield characteristics of another circuit. This method can be thought of yield mapping which utilizes a linear mapping transformation between a critical RF performance parameter and the measured device process control monitor (PCM) data. This transform is known to be used to map PCM data into circuit performance space. Any distribution of PCM parameters are transformed into a distribution of RF performance. An example of such a transformation is shown in
FIG. 3
which illustrates a transformation of a device PCM to MMIC RF performance space. To apply the yield map design to other circuits, an offset is included to account for differences associated with design. Such empirical methods are known to provide accurate forecasting of noise figure and small signal gain performance but not for power. An exemplary comparison of forecasted and measured noise figure performance for a 35 GHz GaAs pHEMT LNA is shown in
FIG. 4
in which the forecasted data is shown with a line and measured data is shown by squares.
One drawback to yield mapping is that it cannot be used to accurately predict RF performance before the designs are produced. Instead its prediction must be refined as the design dependent offset becomes determined through feedback from the pre-production run.
Other empirical methods are known for forecasting RF yield parameter extraction using measured S-parameters. In such methods, the semiconductor device is modeled and parameters are extracted from the measured S-parameters using analytical techniques, for example, as disclosed in “A Semianalytical Parameter Extraction of a SPICE BSIM 3v3 for RF MOSFET's using S-Parameters”, by Lee, et al.,
IEEE Transactions on Microwave Theory and Techniques,
Vol. 48, No. 3, March 2000, pp. 4-416. Unfortunately, such a technique does not provide sufficiently accurate results to accurately forecast RF yield.
Unfortunately, to accurately model the characteristics of a semiconductor device, phenomenon associated with the internal structure of the device, such as, the length of the linear conductance region; the magnitude of saturating electrical fields; the effective transit distance for saturated carriers; and the like need to be considered. Finite element device simulations have been known to be used to calculate the internal electrical charge/electrical field structure of devices. Unfortunately, such device simulations are generally not

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