Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-08-31
2002-07-09
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S210130
Reexamination Certificate
active
06418054
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a scheme and methodology for programming and erasing reference cells in Flash memory devices. The invention is more particularly related to a scheme that utilizes existing flash memory circuitry for the programming of reference cells to attain a threshold voltage appropriate for reference verification of array cell read, program, and erase operations. The invention is also particularly related to a method for performing the programming of reference cells utilizing gate voltages and comparisons of array cell and reference cell voltages and currents.
2. Description of the Related Art
A typical flash memory device
100
is illustrated in FIG.
1
. The flash memory device includes an array of flash cells (array cells or array)
110
, an embedded state machine
120
, a reference array
130
, and sensing circuits
140
. The embedded state machine controls the flash memory device
100
, including operations such as addressing (activation of word lines and bit lines) for reading, programming, or erasing flash memory cells, and applying appropriate voltages to the array cells being programmed. Flash memory devices typically include arrays having 1 Mbit to 64 Mbit or more flash cells.
The flash cells themselves are generally known, and the term “flash” refers to EEPROMs having data written to them, or programmed, by a process known as a hot electron injection, and being erased by Fowler-Nordheim (FN) tunneling. The operation and structure of such devices is discussed in IEEE Journal of Solid State Circuitry, Vol. SC-22, No. 5, October, 1987, pages 676-683, in an article entitled, “A 128K Flash EEPROM Using Double Polysilicon Technology”, by Gheorghe Samachisa, et al.
Flash EEPROM memory cells are generally formed on a semiconductor substrate having diffused therein a N+ drain region and the double diffused source region. A tunnel oxide is formed on the silicon substrate separating a floating gate from the source and drain regions, and a control gate is separated from the floating gate by another insulating layer. The source regions of individual memory cells (for one row of an array, for example) may be connected together and behave as one electrical terminal, or in other arrangements depending on the configuration of the cells.
According to conventional operation, flash EEPROM memory cells are programmed by inducing hot electron injection of electrons from the channel region near the drain to the floating gate (voltages are applied to the gate and drain, and the source is grounded, causing electrons to migrate to the floating gate). Electron injection will carry a negative charge onto the floating gate of a programmed cell. Erasing of flash EEPROM memory cells is typically carried out by Fowler-Nordheim tunneling between the floating gate and the source (known as source erase or negative gate erase) or between the floating gate and the substrate (known as channel erase).
Either programming or erasing of flash cells result in a non-volatile V
T
of the associated programmed or erased cell. A typical flash cell is illustrated in FIG.
2
. The flash cell
200
is a floating gate transistor, the floating gate
210
having either a programmed, erased, or natural V
T
threshold. V
GS
is the voltage applied between the gate and the source, and I
DS
is the current (if any) flowing from the drain (
240
) to source (
230
).
The embedded state machine
120
utilizes reference cells in the reference array
130
to provide reference voltages for the flash memory operations (reading, programming, erasing, and verifying, for example). A state of a selected array cell is compared to the state of a reference array specifically programmed for the operation being performed.
To determine whether or not a specific cell(s) in array
100
has/have been programmed or erased properly, or to read any specific cell(s) in the array, cells in the reference array are utilized to compare the V
T
of the specific cell(s). Sensing circuits
140
are provided for performing a comparison between individual cells of the array
110
and the reference array
130
. The basic process is illustrated in
FIG. 3
, where a selected line
310
(from a selected array cell) from array
110
and a selected line
320
(from a selected reference cell having a V
T
programmed for the operation being performed) from reference array
130
are provided to a comparator
300
of sensing circuit
140
. Again, the selection of specific array cells and reference cells for comparison is generally under the control of the state machine
120
.
One possible configuration of electronics for reading a row of flash cells in the array
110
is illustrated in
FIG. 4. A
word address
405
is input from state machine
120
to a word select
400
that provides a V
SEL
to each of a referenced cell
410
(part of reference array
130
), and flash cells
420
-
1
. . .
420
-(n−1) (part of array
110
). A comparison circuit
430
then compares the current flow of each flash cell
420
-
1
. . .
420
-(n−1) against the current flow of reference cell
410
.
The reference cell
410
is typically one of a set of reference cells maintained in the reference of array
130
. Each reference is generally utilized for comparison of one specific operation (or mode of operation) for the entire array.
During manufacture of the flash cell devices, the reference cells are programmed to have a V
T
appropriate for the comparison function to be performed. This programming of reference cells is commonly performed during a test time of the flash device after fabrication.
It is important that reference cells are programmed to precise V
T
levels to assure accurate and reliable operation of flash memory devices. The manufacturing environment is well suited to perform such programming because accurate voltages and controlled conditions are available to assure that the V
T
of each reference cell is programmed at a precise level. The programming of reference cells can be done utilizing any of the above described techniques (hot electron injection, and/or Fowler-Nordheim tunneling, for example).
However, the processes of programming the reference cells are cumbersome and time-consuming. Currently, a tester controls the sequence externally, inputting a voltage and measuring a current after any number of programming pulses intended to bring the reference cell being programmed to a desired threshold (V
T
). The procedure is time intensive and a large percentage of total sort time is dedicated to reference cell programming.
SUMMARY OF THE INVENTION
The present inventor has realized the need to reduce test and sort time associated with the programming of reference cells. The present invention provides a scheme whereby cells (from flash memory or other semiconductor devices) may be programmed utilizing internal circuitry to perform the programming at accurate levels and a reduction of test time.
The present invention utilizes existing state machine logic, existing word, bit, and reference lines, and existing sensing circuitry to program reference cells to a desired threshold value (V
T
). The present invention provides programming lines to the reference cells so that the V
T
's of the reference cells may be altered via the same methodologies utilized to program array cells. Typical flash memory devices already have array cell/reference cell sensing mechanisms in place and these are then utilized to sense the programmed state of the reference cells.
The present invention provides various methods for sensing whether the flash cells have been programmed to the desired threshold (V
T
), including a comparison of currents using a V
GS
method, and a direct measurement of V
T
via measurement of a V
GS
that allows a programmed reference to conduct a small current source.
The present invention includes programming the reference cells to a V
T
within a specified margin of their natural V
T
level. The present invention performs this by utilizing the &Dgr;
GS
method for p
Advanced Micro Devices , Inc.
Fliesler Dubb Meyer & Lovejoy
Le Vu A.
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