Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element
Reexamination Certificate
1998-09-11
2003-12-30
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Including integrally formed optical element
Reexamination Certificate
active
06670209
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of LCD integrated circuit devices, and more particularly, to a method of passivating the passivation layer of an LCD integrated circuit device in order to maintain a uniform gap height between the top and bottom substrates.
(2) Description of the Prior Art
Liquid crystal displays (LCD) have been used in the art for such applications as computer and television screens. Typically, the topmost level fabricated on a bottom substrate is a series of metal pixels, each pixel 19×19 microns in area. There are typically 1024×768 pixels having a spacing of 0.7 microns between each pixel. The liquid crystal display layer is built on this array of metal pixels and enclosed by a top substrate comprising a transparent material.
FIG. 1
illustrates a LCD integrated circuit device of the prior art. Bottom semiconductor substrate
10
is illustrated. First metal lines
22
are formed overlying a barrier/glue layer
20
. An anti-reflective coating (ARC) layer
24
may be formed over the metal lines
22
. An insulating layer
26
is deposited over the metal lines. Openings are patterned in the insulating layer
26
. The openings are filled with tungsten which is etched back to form tungsten plugs
28
. A second level of metal lines
32
, usually an aluminum alloy, are formed overlying a second barrier layer
30
. The aluminum alloy is separated and protected by a passivation layer, typically 1000 Angstroms of undoped silicate glass (USG)
34
followed by 2500 Angstroms of silicon nitride
36
. The liquid crystal material
52
is sandwiched between the passivation layer and the top substrate
56
.
For sharp display, high speed, and good performance, it is critical that the liquid crystal maintain a constant gap between the top and bottom substrates. The crucial gap height is not maintained in the process of the prior art. As seen in
FIG. 1
, the height A above the metal pixels is not the same as the height B between the metal pixels.
There are a number of patents in the field of LCD's. For example, U.S. Pat. No. 5,696,386 to Yamazaki, U.S. Pat. No. 5,708,486 to Miyakawaki et al, and U.S. Pat. No. 5,868,790 to Curtain et al discuss LCD formations in which the gap width is non-constant. U.S. Pat. No. 5,056,895 to Kahn teaches an insulating leveling layer of polymer or spin-on-glass. U.S. Pat. No. 5,721,601 to Yamaji et al discloses a spin-on-glass planarizing film. U.S. Pat. No. 5,592,318 to Majima et al teaches planarizing with a polyimide resin.
U.S. Pat. No. 5,635,423 to Huang et al and U.S. Pat. No. 5,578,523 to Fiordalice et al teach dual damascene processes to form a plug and trench and fill them with a single conducting material. Damascene is an art which has been used for centuries in jewelry making and which has been used recently in the semiconductor industry. Damascene involves the formation of a trench which is filled in with metal and then planarized.
SUMMARY OF THE INVENTION
Accordingly, a primary object of the invention is to provide a process for maintaining a uniform gap between the passivation layer of a bottom substrate and the top substrate of a LCD integrated circuit device.
A further object of the invention is to provide a process for forming a planarized metal layer in the fabrication of an integrated circuit device.
Another object is to provide a process for forming a planarized metal layer in order to maintain a uniform gap between the passivation layer of a bottom substrate and the top substrate of a LCD integrated circuit device.
Yet another object of the invention is to provide a process for forming a planarized metal layer by forming the plug and overlying metal interconnect simultaneously in order to maintain a uniform gap between the passivation layer of a bottom substrate and the top substrate of a LCD integrated circuit device.
Yet another object of the invention is to provide a process for forming a planarized metal layer by using a dual damascene process in order to maintain a uniform gap between the passivation layer of a bottom substrate and the top substrate of a LCD integrated circuit device.
In accordance with the objects of the invention, a process for forming a planarized metal layer by forming the plug and overlying metal interconnect simultaneously in order to maintain a uniform gap between the passivation layer of a bottom substrate and the top substrate of a LCD integrated circuit device is achieved. Semiconductor device structures are formed in and on a semiconductor substrate wherein the semiconductor device structures are covered by an insulating layer. A trench is patterned into the insulating layer and a via opening is made within the trench through the insulating layer to one of the underlying semiconductor device structures. A metal layer is deposited overlying the insulating layer and within the trench and via opening. The metal layer overlying the insulating layer is polished away leaving the metal layer within the trench to form a metal pixel and within the via opening to form an interconnect between the metal pixel and the underlying semiconductor device wherein the top surface of the substrate is planarized. A passivation layer is deposited overlying the top surface of the substrate. A liquid crystal material layer is formed overlying the passivation layer and sandwiched between the bottom substrate and a second semiconductor substrate to complete the fabrication of the liquid crystal display integrated circuit device.
REFERENCES:
patent: 5056895 (1991-10-01), Kahn
patent: 5578523 (1996-11-01), Fiordalice et al.
patent: 5592318 (1997-01-01), Majima et al.
patent: 5635423 (1997-06-01), Huang et al.
patent: 5686790 (1997-11-01), Curtin et al.
patent: 5696386 (1997-12-01), Yamazaki
patent: 5708486 (1998-01-01), Miyawaki et al.
patent: 5721601 (1998-02-01), Yamaji et al.
patent: 5960317 (1999-09-01), Jeong
patent: 6025269 (2000-02-01), Sandhu
Chartered Semiconductor Manufacturing Ltd.
Coleman W. David
Pike Rosemary L. S.
Saile George O.
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