Embedded isolation region and process for forming the same on si

Details Embedded isolation region and process for forming the same on si Embedded isolation region and process for forming the same on si

1989-09-14

1990-11-06

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 26, 437 61, H01L 2176

Patent

active

049686364

ABSTRACT:
An embedded isolation region and a process for forming the same on the substrate made of silicon. The isolation region(s) is constituted of a silicon nitride region, a silicon oxide region and, if required, a channel stop region in this order in the upper surface of the substrate to the deep inside of the substrate. The isolation region(s) is formed by an ion implantation technique using a mask made of an oxide film, followed by oxidation and removal of at least an upper substrate region on the upper side of the silicon nitride region. As compared with the formation of a conventional trench type region(s), even isolation regions with different sizes or an isolation region having portions with different sizes can be formed without a fear of entailing an uneven surface, and the development of crystal defects can be mitigated without an increase in the number of steps, while, even in a trench filled with poly-Si, at the same time some adverse effect of the remaining poly-Si on element regions can be avoided.

REFERENCES:
patent: 3622382 (1971-11-01), Brack et al.
patent: 3976511 (1976-08-01), Johnson
patent: 4800170 (1989-01-01), Jain et al.
A New Trench Isolation Technique for MOS VLSI, Toshiyuki Ishijima and Kazuo Terada.

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