Coherent light generators – Particular active media – Liquid
Reexamination Certificate
1999-02-01
2001-02-27
Tran, Toan (Department: 2816)
Coherent light generators
Particular active media
Liquid
C327S052000
Reexamination Certificate
active
06195377
ABSTRACT:
BACKGROUND OF THE INVENTION
Generally speaking, computer systems typically include one or more central processor units (CPUs). Each CPU includes many signal paths that convey data between functional units that operate on that data. Such data is typically conveyed using a transfer cycle having a specified timing structure. That timing structure dictates a time period when the data to be transferred will be valid. Accordingly, the data is captured or latched while it is valid and held for a specified amount of time. Such data capture can be performed using a number of edge triggered latches that sense and subsequently latch that data.
Within a CPU, edge triggered latches are commonly implemented using a circuit referred to as a “sense amplifier”. Sense amplifiers are designed to sense the logic level of a data signal and to output a steady or latched version of that logic level. Because an edge triggered latch typically samples or “senses” the data on the rising edge of a clock cycle, the above mentioned time period is typically specified with respect to the particular clock cycle during, which the data is valid. The data is latched, i.e. held at the output of the sense amplifier, until the falling edge of that clock cycle or until the rising edge of the next clock cycle, depending upon its design. After that data has been latched, new data can be asserted on the signal line without affecting the latched data.
An ideal sense amplifier would latch the data immediately upon the rising edge of the associated clock cycle. In practice, however, the latching operation occurs over a finite amount of time during which the data must remain stable. That finite amount of time is defined by “data set-up” and “data hold” timing requirements. Accordingly, the data signal presented to the sense amplifier must satisfy the data set-up and data hold timing requirements in order for the associated logic levels to be properly latched.
The data set-up timing requirement refers to the amount of time that the data must remain stable before the sense amplifier latches it. The data set-up time is typically specified in relation to the rising edge of the above mentioned clock cycle during which the data is valid. The data hold timing requirement refers to the amount of time that the data signal must remain stable after the rising edge of that same clock cycle.
Logic circuits arc typically connected in series with such sense amplifiers so that associated logic functions can be performed on the incoming data before it is latched. For example, before being input to a sense amplifier, a pair of data signals may be logically “Anded”. The product of those data signals is then conveyed to the sense amplifier which responsively senses the product and generates a corresponding latched output signal. The circuits that implement such logic functions impose a time delay, referred to as the “propagation delay,” that is measured from the time when the data signals are imposed on the circuit until the product is generated. The propagation delay defers the point in the data cycle when the data is received by the sense amplifier and thus defers the point when the latching operation can be initiated. Therefore, in order for the data to satisfy the set-up and hold timing requirements of the sense amplifier, the data needs to remain valid at the input of the logic function for a time period that is at least as long as the combination of the propagation delay of the logic circuit and the set-up and hold timing requirements of the sense amplifier.
SUMMARY OF THE INVENTION
The data set-up timing requirement of prior art sense amplifiers is effectively increased by the propagation delay of the logic circuits that are connected in series therewith. In other words, data that is to be operated on by the logic circuit, and subsequently latched by the sense amplifier, must be held stable for a substantially longer time than data that is directly input to the sense amplifier. Therefore, the data set-up timing requirement of the sense amplifier is effectively increased by the propagation time of the logic circuit, thereby reducing the performance of that sense amplifier.
Accordingly, a method and apparatus are provided for improving the effective data set-up timing requirement of the sense amplifier. Specifically, the logic function is incorporated into the sense amplifier such that the propagation time of the logic function is avoided and the effective data set-up time of the sense amplifier is reduced.
In accordance with an embodiment of the present invention, a method and apparatus is provided for imposing a logic function on a plurality of data signals, as part of the latching operation. The sense amplificr achieves that result by discharging an internal signal through a first discharge path when a first logic function is asserted. That logic function is included as an integral portion of the discharge path rather than as a separate logic circuit. Also, another internal signal is discharged through a second discharge path when a second logic function, included as an integral portion of that discharge path, is asserted. The second logic function is asserted in response to a generated representation of the data signals.
When the representation is a buffered representation, the logic function associated with the second discharge path is the logical inversion of the logic function associated with the first discharge path. Accordingly, the logic functions arc asserted and de-asserted at complementary times. For example, the logic function associated with the second discharge path may be a logical NAND, NOR or XNOR function when the logic function associated with the first discharge path is a logical AND, OR or XOR function, respectively.
When the representation is an inverted representation, the combination of that inversion with the logic function associated with the second discharge path, performs the complementary logic function to the logic function associated with the first discharge path. For example, that logic function may be implemented as a logical NAND, NOR or XNOR function when the logic function associated with the first discharge path is a logical AND, OR, or XOR function, respectively. In other words, the logic function that is associated with the second discharge path is asserted when the logic function associated with the first discharge path is deasserted, and vice versa.
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Bell Shane Lewis
Gieseke Bruce Alan
Digital Equipment Corporation
Hamilton Brook Smith & Reynolds P.C.
Nguyen Hiep
Tran Toan
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