Embedded EEPROM array techniques for higher density

Details Embedded EEPROM array techniques for higher density Embedded EEPROM array techniques for higher density

2005-09-19

2008-12-30

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185140

Reexamination Certificate

active

07471570

ABSTRACT:
An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM layout that eliminates the use of high voltage transistors from the array core region. If they are utilized, the high voltage transistors are moved to row and column drivers in the periphery region to increase array density with little or no added process complexity to allow economic implementation of larger embedded SLP EEPROM arrays. During program or erase operations of the array, the method provides a programming voltage for the selected memory cells of the array, and a half-write (e.g., mid-level) voltage to the remaining unselected memory cells to avoid disturbing the unselected memory cells of the array.

REFERENCES:
patent: 5642295 (1997-06-01), Smayling
patent: 5917222 (1999-06-01), Smayling et al.
patent: 6157058 (2000-12-01), Ogura
patent: 6272584 (2001-08-01), Stancil
patent: 6487139 (2002-11-01), Pathak
patent: 6574140 (2003-06-01), Caywood
patent: 6862223 (2005-03-01), Lee et al.
patent: 2003/0127694 (2003-07-01), Morton et al.
patent: 2003/0235080 (2003-12-01), Yaegashi et al.
patent: 2004/0141374 (2004-07-01), Park et al.
patent: 2005/0078521 (2005-04-01), Chen et al.
patent: 2005/0088890 (2005-04-01), Matsunaga et al.
patent: 2005/0104119 (2005-05-01), Diorio et al.
patent: 2005/0117378 (2005-06-01), Cho et al.
patent: 2005/0145922 (2005-07-01), Farley et al.
patent: 2005/0169052 (2005-08-01), Hsu et al.
patent: 2005/0248987 (2005-11-01), Shone
U.S. Appl. No. 10/910,210, filed Aug. 2, 2004, Mitros et al.

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