Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer data framing
Reexamination Certificate
2007-09-04
2007-09-04
Wiley, David (Department: 2143)
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
Computer-to-computer data framing
C709S250000, C709S212000, C714S749000, C370S389000
Reexamination Certificate
active
10259409
ABSTRACT:
An host channel adapter embedded within a processor device includes a transport layer module, a transport layer buffer, a link layer module, and a link layer buffer configured for storing at least two packets to be transmitted by the embedded host channel adapter. The transport layer module is configured for generating, for each packet to be transmitted, a transport layer header, and storing in the transport layer buffer the transport layer header and a corresponding identifier that specifies a stored location of a payload for the transport layer header. The link layer module includes payload fetch logic configured for fetching the payload based on the corresponding identifier, enabling the link layer module to construct one of the two packets to be transmitted concurrently during transmission of the second of the two packets.
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Bailey Joseph A.
Hack Norman M.
Winkles Joseph D.
Advanced Micro Devices , Inc.
Jean-Gilles Jude
Manelli Denison & Selter PLLC
Turkevich Leon R.
Wiley David
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