Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-06-20
2002-12-03
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C156S345300, C156S915000, C216S067000, C438S710000
Reexamination Certificate
active
06489249
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to the modification of apparatus to cause elimination or reduction of black silicon during a DT (deep trench) etching process during fabrication of integrated circuits (ICs) or chips, in which there is etching into a silicon substrate features used to form microelectronic devices. In particular, the invention relates to the elimination or reduction of black silicon during the DT etch which may serve as a trench capacitor of a memory cell, by causing sheath shaping on the lower electrode assembly in an etching reactor.
2. Description of the Related Art
Integrated circuit (IC) technology has recently moved from large-scale integration (LSI) to very large scale integration (VLSI) and is expected to grow to ultra-large scale integration (ULSI) in the very near future. These advancements in monolithic circuit integration is possible by virtue of improvements in manufacturing equipment and the materials and methods used in preparing semiconductor wafers into IC chips.
Several factors impose increasingly strict requirements on the basic integrated circuit fabrication steps of: masking; film formation; doping and etching; and dielectric insulation.
These factors are: the incorporation of IC chips of increasingly complex devices and circuits; the use of greater device densities and smaller feature sizes, and smaller separation; the use of composite conductor layers; and the use of the third wafer dimension of depth as well as the surface area to form buried or trench capacitors (DT).
In this connection, the ability to etch narrow, deep, high aspect ratio trenches is vital to the formation of buried or trenched capacitors. Further, single crystal silicon trench isolation is increasingly being used in semiconductor research as an alternative to other device isolation technologies, due to the fact that trench dielectric isolation offers a number of advantages, such as relatively small surface area requirements, small width-to-depth ratios, and a vertical wall profile.
A further and significant advantage of the trench technology is its relative simplicity of process. For example, to create a buried capacitor or dielectric isolation structure using trench technology entails reactive ion etching (REI) a groove into a single crystal silicon substrate, oxidizing side walls of the groove or trench, filling the groove with oxide dielectric or a polysilicon, and planarizing the surface.
However, “black silicon” is one of the prevalent etch obstacles during the etching process. Black silicon is caused by the presence of surface contaminates such as residual oxides, that act as localized etched mask. Consequently, the areas beneath these micromasks are not etched away until the contaminates are completely eroded, thereby causing the bottom of the finished trenched substrate to develop a rough, light-scattering dark surface appearance that is responsible for the name “black silicon”.
Black silicon formation at the edge of a wafer can also cause loss of chips and therefore directly contributes to chip yield loss.
One of the mechanisms for black silicon formation is the erosion of the boron doped silicate glass (BSG) mask at the edge that causes the exposure of the silicon surface. The higher BSG/Nitride etch rate at the periphery of the wafer is caused by the focusing of ions from the focusing dielectric ring placed around the wafer in the DT (deep trench) etch tool.
U.S. Pat. No. 5,874,362 disclose a method for etching a high aspect ratio, straight walled opening in silicon, in which the opening is characterized by a rounded bottom. The process is conducted by forming a plasma from a precursor gas etch mixture of HBr as the main etchant, using oxygen to provide protection for the side walls of the openings and to control selectivity with respect to the oxide etch mask, employing a fluorine-containing gas to remove residual contaminates from the side walls of the openings, and etching a silicon body until an opening of the desired depth is formed. The use of a brominate and gas chemistry in this process is said to overcome the problem of black silicon.
A method of and apparatus for improving etch uniformity in remote source plasma reactors with a powered wafer chuck or pedestal is disclosed in U.S. Pat. No. 5,662,770. The invention addresses the uniformity problem which arises due to non-uniform power coupling between a wafer and the walls of the etch chamber by increasing the impedance between the wafer and the chamber walls by placing a cylindrical dielectric quartz wall around the wafer if silicon is to be etched selectively with respect to silicon dioxide.
A plasma etch apparatus with heated scavenging surfaces is disclosed in U.S. Pat. No. 5,477,975. The plasma etch reactor is operated by introducing a gas into the reactor which disassociates as a plasma into an etched species which etches oxide films on a work piece in the reactor and a non-etching species combinable with the etched species into an etch-preventing polymer condensable onto the work piece below a certain deposition temperature, thereby providing an interior wall comprising a material which scavenges the etching species, and maintains a temperature of the interior wall above the deposition temperature.
U.S. Pat. No. 5,292,399 disclose a plasma etching apparatus with conductive means for inhibiting arcing. The conductive means for inhibiting arcing from electrical charges accumulating on one or more non-conductive protective surfaces on members at Rf potential within the apparatus includes one or more conductive plugs extending through one or more of the protective surfaces or a conductive ring surrounding the wafer on the top surface of a metal pedestal.
Accordingly, there is a need in the art of fabricating integrated circuits or chips, where features are created by etching into the silicon substrate deep trenches (DT) which serve as a trench capacitor, to flatten the self-developed negative dc bias (Vdc) sheath boundary beyond the edge of the wafer, and thereby reduce DT mask erosion at the wafer periphery to eliminate or reduce “black silicon” in the DT etch.
There is a further need in the art of fabricating integrated circuits or chips where features are created by etching into the silicon substrate a deep trench that serves as a trench capacitor, to reduce DT mask erosion by utilizing a silicon source to provide a deposition component at the edge of the wafer, to assist in the elimination or reduction of black silicon in the DT etch.
SUMMARY OF THE INVENTION
In general, the invention relates to utilizing an electrode configuration with a focusing sheath of a lower electrode assembly in an etching reactor through an innovation that flattens the sheath at the wafer periphery, to effectively defocus ions from the boundary of the self-developed negative dc bias (Vdc). Towards this end, a disc, preferably of silicon, is added to modify an existing quartz ring used as an insulator that is not easily eroded by the etching environment, and the silicon disc is easily replaced without replacing the entire wafer chuck/clamping ring mechanism. By shaping the Vdc sheath at the wafer surface to defocus the ions and thereby reduce the erosion of the BSG mask, elimination and/or reduction of black silicon is accomplished in the DT etch.
One object of the present invention is to provide a modification to the typical electron configuration with focusing sheath used in DT etch to fabricate integrated circuits or chips in which the features created by etching into a silicon substrate are those which are deep trench (DT) features that serve as trench capacitors.
Another object of the present invention is to provide a modification of the typical electron configuration with focusing sheath used in the fabrication of integrated circuits or chips in which features are created by etching into a silicon substrate a deep trench which serves as a trench capacitor, by flattening the sheath at the wafer periphery to effectively defocus the ions that accelerate across the
Mathad Gangadhara S.
Ranade Rajiv
Infineon - Technologies AG
Stanton Braden
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