Elimination of stacking faults in silicon devices: a gettering p

Details Elimination of stacking faults in silicon devices: a gettering p Elimination of stacking faults in silicon devices: a gettering p

1975-06-24

1976-12-14

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148175, 148188, H01L 21265

Patent

active

039973689

ABSTRACT:
Described are procedures for fabricating silicon devices which prevent the formation and/or activation of stacking fault nucleation sites during high temperature processing steps, such as steam oxidation of silicon wafers. The procedures, which take place before such high temperature steps, include forming on the back surface of the wafer a stressed layer and then annealing the wafer for a time and at a temperature effective to cause the nucleation sites to diffuse to a localized region near to the back surface. Illustratively the stressed layer comprises silicon nitride or aluminum oxide. Enhanced gettering is achieved if, prior to forming the stressed layer, interfacial misfit dislocations are introduced into the back surface by, for example, diffusion of phosphorus therein. Following the gettering step(s) on the back surface, conventional procedures, such as growing epilayers and/or forming p-n junctions, are performed on the front surface of the wafer.

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Barson, et al. "Gettering Technique", IBM Tech. Dis. Bull., vol. 15, No. 6, Nov. 1972, p. 1752.

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