1974-12-30
1976-05-04
James, Andrew J.
357 43, 357 48, 357 52, 357 86, H01L 2702
Patent
active
039552101
ABSTRACT:
A complementary field effect transistor structure which eliminates the problems caused by parasitic currents between devices. The currents are contained within parasitic bipolar devices formed between the various regions of the FETs. A portion of the collector current of the parasitic bipolar devices is drained away so that the loop gain is less than one. This is achieved by placing guard regions of conductivity type which are the same as the channel type of the transistors adjacent said regions. The guard region is preferably in the form of a continuous ring around its associated FET.
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patent: 3798512 (1974-03-01), Critchlow et al.
patent: 3806371 (1974-04-01), Barone
patent: 3916430 (1975-10-01), Heunter et al.
H. Kalter, "Bipolar and FET Integration on a Common Chip," IBM Tech. Discl. Bull., Vol. 15, No. 12, May 1973, pp. 3755-3756.
W. Dennehy, "Non-Latching Integ. Ckts.," R.C.A. Tech. Notes, No. 876, 2-12-71, pp. 1-4.
Bhatia Harsaran Singh
O'Rourke Gerald Dennis
Wiedmann Siegfried K.
Clawson Jr. Joseph E.
Galvin Thomas F.
International Business Machines - Corporation
James Andrew J.
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