Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-04-03
2004-11-09
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S761000, C257S635000
Reexamination Certificate
active
06815367
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of manufacturing a wafer stack comprising a deep trench (DT) level, wherein the deposited TERA hardmask has a substrate reflectivity below 0.8 percent, but wherein the resist printed on to wafer is free from creating an interaction between the resist-hardmask, and is therefore free from the disadvantage of “footing”.
2. Description of the Related Art
Increased demand for high performance in semiconductor devices has necessitated smaller ground rules, in part, to permit increased processing speed. Consistent with the demand for high performance semiconductor devices, is the corollary of finer and finer patterning of resist images to attain higher integration. To satisfy this requirement, development and improvement of lithographic techniques using short-wave length exposure tools such as deep-ultraviolet (DUV) has been employed.
Photoresists (resists) are photo sensitive films that are used for transfer of an image to a substrate, and entails coating the photoresists on a substrate and exposing it through a photomask to a source of activating radiation. The photomask is comprised of areas that are opaque to activating radiation and other areas that are transparent to activating radiation. The exposure to activating radiation creates a photoinduced chemical transformation of the photoresist coating to transfer a pattern from the photomask to the photoresist coated substrate. After exposure the photoresist is developed to form a relief image that allows selective processing of the substrate.
The photoresist may be either positive-acting or negative-acting. In the negative-acting photoresists coating the layer portions that are exposed to activating radiation crosslinks or polymerizes a reaction between a photoactive compound and polymerizable reagents of the photoresist, so that exposed coating portions are made less soluble in a developer solution than unexposed portions.
For a positive-acting photoresist, exposed portions are made more soluble in a developer solution while areas not exposed are less soluble in the developer solution.
Proper photoresist processing is one of the keys to obtaining a small ground rule, efficient wafer stack for a DT level on the semiconductor.
Unfortunately, at the critical levels required for high performance semiconductor devices where density lines are required to be increased for a wafer stack for a DT level, a single layer resist approach cannot fulfill both the lithography and etch requirements, due to the fact that, even though use of a TERA hardmask produces a substrate reflectivity below 0.8 percent without any standing waves, nevertheless, a resist-hardmask interaction occurs that results in “footing”.
Lee et al.,
Inorganic ARC for
0.18
&mgr;m and Sub
-0.18
&mgr;m Multilevel Interconnects
1998 IEEE 98, 84-86 disclose a novel designed inorganic ARC for deep-UV lithography and implementation of the ARC into multi-level metal interconnects for sub-micron technologies using Si
x
O
y
N
z
ARC to reduce substrate reflectivity to a minimum and prevent DUV resist footing, while allowing the novel ARC to serve as a hardmask for metal etch.
In-situ hardmask and metal etch in a single etcher to develop a semiconductor device with a layer of photoresist patterned and developed free from resist footing is disclosed in U.S. Pat. No. 6,159,863. The process entails:
forming active devices in and on a substrate in the semiconductor wafer;
forming an interlayer dielectric on a surface of the semiconductor wafer;
forming a metal layer on the surface of the interlayer dielectric;
forming a layer of hardmask material on the surface of the metal layer;
forming a layer of photoresist on the layer of hardmask material;
patterning and developing the layer of photoresist exposing portions of the hardmask material underlying the layer of photoresist;
placing the semiconductor wafer in an etcher;
etching the exposed portions of the layer of hardmask material exposing portions of the metal layer
underlying the layer of hardmask material; and
without removing the semiconductor wafer from the etcher etching the exposed portions of the metal layer.
U.S. Pat. No. 6,261,743 B1 disclose a method of forming a photoresist relief image that substantially reduces “notching” and “footing” comprising:
(a) applying on a substrate a layer of an antireflective composition comprising a photoacid generator
compound, an acid or thermal acid generator compound and a crosslinker, and crosslinking the antireflective layer;
(b) applying a layer of the photoresist composition over the antireflective composition layer;
(c) exposing the photoresist layer to activating radiation whereby the photoacid generator of the antireflective composition generates acid; and
(d) developing the exposed photoresist.
In manufacturing a wafer stack comprising a deep trench (DT) level, in which a hardmask is deposited on a substrate to provide the necessary reflectivity below 0.8%, there is a need to enable a single layer resist (SLR) printed on the wafer, in which there are no standing waves, to also prevent interaction between the resist-hardmask that leads to footing and the drawbacks attendant thereto.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a process to manufacture a wafer stack, wherein the hardmask deposited on the substrate has a reflectivity below about 0.8%, so that a single layer resist (SLR) printed on the wafer shows no standing waves, and prevents interaction between the resist-hardmask, to thereby alleviate “footing” or the failure to clear during development that results in an upwardly tapering release image sidewall.
In general, the invention is accomplished by forming a layer of hardmask material on a photoresist disposed on a substrate; subjecting the hardmask to an oxidation step to form a cap; depositing a layer of SiO
2
on top of the cap layer; and patterning and developing the layer of photoresist to obtain a substrate reflectivity below 0.8%, without the occurrence of “standing waves”, and without “footing”.
REFERENCES:
patent: 5830605 (1998-11-01), Umeki et al.
patent: 5886102 (1999-03-01), Sinta et al.
patent: 6159863 (2000-12-01), Chen et al.
patent: 6261743 (2001-07-01), Pavelchek et al.
patent: 6300240 (2001-10-01), Linliu et al.
patent: 6303275 (2001-10-01), Coles et al.
patent: 6329117 (2001-12-01), Padmanaban et al.
patent: 6518200 (2003-02-01), Lin
patent: 6573189 (2003-06-01), Lin et al.
Fahmy Wael
Infineon - Technologies AG
Peralta Ginette
LandOfFree
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