Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2002-08-02
2003-07-29
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C326S081000
Reexamination Certificate
active
06600358
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to level shifters for shifting from one voltage level or power domain to another. In particular, it relates to a way of avoiding current drain in the higher power domain when the lower power domain is off.
BACKGROUND OF THE INVENTION
Semiconductor devices such as VLSI chips, it is common to have more than one voltage level or power domain. In order to be able to correctly handle signals passing from one power domain to another, level shifter circuits are included to convert the voltage level of the signal so as to correctly work with the devices in the new power domain. For instance, where a transition is made from a power domain operating at a low voltage level (VDDL) of 1.2 V to a higher power domain operating at a higher voltage (VDDH) of 3.3 V, a high input signal of 1.2 V would not necessarily be interpreted in the high power domain as a high logic level. It is therefore necessary to adjust the voltage level of the input signal to be correctly interpreted in the new power domain. This is achieved through the use of a level shifter such as the step up level shifter
100
shown in FIG.
1
.
The level shifter
100
has an input
102
working at a low power level (VDDL) and an output
104
which supplies an output signal as dictated by the higher voltage (VDDH) of the higher power domain. A logic high signal will switch on transistor
106
, thereby pulling node B to ground and switching transistor
108
on. This pulls node A high to the voltage level VDDH. The logic high passes through the two inverters
110
,
112
to provide a high output signal in accordance with the high power domain requirements.
During a logic low on the input
102
, the inverter
120
provides a high signal to the transistor
122
to switch transistor
122
on and pull node A to VSS. This switches on PMOS transistor
124
to pull node B high. This switches off transistor
108
to ensure that node A is low, thereby providing a low output signal at output
104
(as determined by the two inverters
110
,
112
).
However, for power management purposes it is common to turn off parts of a chip. When VDDL is shut off, there will, thus be floating nodes in the level shifter
100
. In particular, when VDDL is turned off, the signal on input
102
becomes indeterminable. Since NMOS transistors
106
,
122
are not being actively driven, nodes A and B float. In the worst case, the nodes A and B could float to half VDDH, thereby causing a static current drain through inverters
110
,
112
. This could adversely affect other gates connected to the output
104
. This can be best understood by considering a simple inverter circuit as shown in FIG.
2
. If VDDH is at 3.3 V, the input to the inverter
200
is at about 1.6 when the floating nodes float to half VDDH. This means that both the PMOS transistor
210
and the NMOS transistor
212
are turned on since the voltage is not high enough to turn off the PMOS transistor
210
, or low enough to turn off NMOS transistor
212
. Thus, there is a static current drain.
The present invention seeks to eliminate this problem.
SUMMARY OF THE INVENTION
The invention provides a circuit to eliminate potential static current drain in a step-up level shifter when the power to the lower potential power domain in a multi-power system is switched off.
Thus, according to the invention, there is provided a method to eliminate static current drain in a level shifter when the power to a low potential power domain VDDL in a multi-power system is switched off, wherein the shifter shifts signal voltages from a low potential power domain VDDL to a high potential power domain VDDH, comprising providing a signal path from the input to the output of the level shifter under power conditions when VDDL is active, and isolating the input from the output when VDDL is off, and providing, from VDDH, a low or high level signal at the output. The provision of the signal from VDDH typically includes a signal generating circuit powered by VDDH. Preferably the method includes isolating the signal generating circuit under power conditions. The method typically includes monitoring VDDL to determine whether VDDL is active.
Further, according to the invention, there is provided a circuit for eliminating static current drain in a level shifter when the power to a low potential power domain VDDL in a multi-power system is switched off, wherein the shifter shifts signal voltages from a low potential power domain VDDL to a high potential power domain VDDH, comprising VDDL monitoring circuitry, isolation circuitry for isolating the input to the level shifter when VDDL is switched off, and signal generating circuitry for generating a signal for the output of the level shifter when VDDL is off. Typically the circuit provides a signal path through the level shifter when VDDL is on. The signal generating circuitry is preferably powered by VDDH and the signal generated is either a high or a low signal for the high potential power domain. The high or low signal is determined according to the nature of the circuitry that receives the signal. The isolation circuitry may be controlled by the monitoring circuitry to isolate the input when the monitoring circuitry detects VDDL is switched off. The isolation circuitry may include a pass gate. The monitoring circuitry may be configured to deactivate the isolation circuitry when VDDL is on. The monitoring circuitry is preferably powered by VDDH. The monitoring circuitry may include voltage step down circuitry to lower the voltage supplied to it. The voltage step down circuitry may include a plurality of strings of one or more transistors connected to VDDH, and at least some of the strings supplying inverters. At least some of the strings may define different voltage step downs. The voltage step down caused by each string of transistors is preferably chosen to ensure that when the input supplied to the associated inverter is high, it is sufficiently high to switch off the PMOS transistor of the inverter. Typically the input to the first inverter is from VDDL. Typically the transistor strings associated with the other inverters are shorter than the first transistor string, to provide for increasing output voltages from successive inverters.
REFERENCES:
patent: 5912577 (1999-06-01), Takagi
patent: 6005432 (1999-12-01), Guo et al.
patent: 6064229 (2000-05-01), Morris
patent: 6147540 (2000-11-01), Coddington
patent: 6188243 (2001-02-01), Liu et al.
patent: 6344758 (2002-02-01), Turner et al.
patent: 6384631 (2002-05-01), Wert et al.
patent: 6385099 (2002-05-01), Taub
patent: 2001/0011917 (2001-08-01), Kim et al.
National Semiconductor Corporation
Tran Toan
Vollrath & Assoc.
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