Elevated transistor fabrication technique

Details Elevated transistor fabrication technique Elevated transistor fabrication technique

2000-06-12

2002-07-16

Prenty, Mark V (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

C257S074000

Reexamination Certificate

active

06420730

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of semiconductor processing and, more particularly, to an integrated circuit and method of making same, wherein a transistor is fabricated a spaced distance above another transistor to produce a higher density of active devices on a wafer.
2. Description of Relevant Art
Fabrication of a metal-oxide-semiconductor (“MOS”) transistor is well-known. Fabrication typically begins by introducing f-type or p-type impurities into a single-crystal silicon substrate. The active regions of the substrate (where the transistors will be formed) are then isolated from each other using isolation structures. In modern fabrication technologies, the isolation structures may comprise shallow trenches in the substrate filled with a dielectric such as oxide which acts as an insulator. Isolation structures may alternatively comprise, for example, locally oxidized silicon (“LOCOS”) structures. A gate dielectric is then formed by oxidizing the silicon substrate. Oxidation is generally performed in a thermal oxidation furnace or, alternatively, in a rapid-thermal-anneal (“RTA”) apparatus. A gate conductor is then patterned using a photolithography/etch process from a layer of polycrystalline silicon (“polysilicon”) deposited upon the gate dielectric. The photolithography process allows selective removal of a photoresist film deposited entirely across the polysilicon. The portion of the photoresist film that is exposed can, according to one embodiment, be polymerized, and that which is not exposed removed during the “develop” stage of the lithography process. The regions that are non-polymerized form a mask for a subsequent etch during which portions of the polysilicon layer that are not masked by the photoresist pattern are removed. After the etch process, the patterned photoresist layer is stripped away.
In the sub micron range, it is very critical to produce gate conductors with substantially vertical sidewalls. The width of the gate conductor determines the channel length of the device, which is very critical to the performance of the device. This is insignificant for devices with longer channel lengths but more critical for submicron devices. It is difficult to produce a polysilicon gate conductor with substantially vertical sidewalls. Sloped sidewalls are common resulting in longer channel lengths.
The polysilicon is typically rendered conductive with the introduction of ions from an implanter or a diffusion furnace. Subsequently, source and drain regions are doped with a high-dose n-type or p-type dopant If the source and drain regions are doped n-type, the transistor is refer to as NMOS, and if the source and drain regions are doped p-type, the transistor is referred to as PMOS. A channel region between the source and the drain is protected from the implant species by the pre-existing gate conductor. When an appropriate bias is applied to the gate of an enhancement-mode transistor, a conductive channel between the source and drain is induced and the transistor turns on.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to form relatively small, closely spaced transistors within a single integrated circuit. Unfortunately, since transistors are generally formed within the silicon-based substrate of an integrated circuit, the number of transistors per integrated circuit is limited by the available lateral area of the substrate. Moreover, transistors cannot employ the same portion of a substrate, and increasing the area occupied by the substrate is an impractical solution to this problem. Thus, packing density of an integrated circuit is somewhat sacrificed by the common practice of forming transistors exclusively within a substrate having a limited amount of area. Having more densely packed transistors would result in an increase in the number of devices, such as central processing units, memory chips, etc., formed on each wafer.
It would therefore be desirable that a semiconductor fabrication process be developed for the formation of more densely packed transistors. Such a process would lead to an increase in circuit speed as well as an increase in circuit complexity.
SUMMARY OF THE INVENTION
The problems identified above are in large part addressed by a semiconductor process in which a second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed into the interlevel dielectric. A second transistor is then formed on the upper of the second semiconductor substrate. The second transistor is a spaced distance above the first transistor. The two transistors are a lateral distance apart which is smaller than the distance that can be achieved by conventional fabrication of transistors on the upper surface of the wafer. Transistors are more closely packed which results in an increase in the number of devices produced per wafer.
Broadly speaking the present invention contemplates a method for fabricating an integrated circuit. A first semiconductor substrate is provided. A first transistor is formed upon the first semiconductor substrate. An interlevel dielectric is deposited upon the first semiconductor substrate and the first transistor. A second semiconductor substrate is formed within the interlevel dielectric. The second semiconductor substrate is laterally and vertically displaced from the first transistor.
A polish-stop layer is deposited upon the interlevel dielectric and the second semiconductor substrate. A portion of the polish-stop layer is removed to form a trench and expose a portion of an upper surface of the second semiconductor substrate. A second gate dielectric layer is formed upon the upper surface of the second semiconductor substrate. A conductive material is deposited within the trench to form a second gate conductor.
The remaining portion of the polish-stop layer may then be removed to expose the second gate conductor. A second concentration of dopants is introduced into the second semiconductor substrate to form a second pair of source/drain regions.
The step of introducing a second concentration of dopants preferably comprises implanting a light concentration of dopants to form a lightly doped portion of the second pair of source/drain regions. A second set of spacers is formed upon a second set of sidewalls of the second gate conductor. A high concentration of dopants is then implanted to form a highly doped portion of the second pair of source/drain regions. A lateral distance of the second pair of source/drain regions from the second gate conductor is defined by the second set of spacer structures.
The first semiconductor substrate comprises a lightly-doped, epitaxial layer of single-crystalline silicon. The step of depositing an interlevel dielectric comprises depositing tetraethyl orthosilicate or silane using chemical-vapor deposition. The interlevel dielectric may be further doped with boron and/or phosphorous.
The step of forming a second semiconductor substrate comprises first etching a trench void into an upper surface of the interlevel dielectric. Polysilicon is then deposited within the trench void, exterior to the trench void, and upon the upper surface of the interlevel dielectric. The polysilicon is then removed from an upper surface of the interlevel dielectric and exterior to the trench void using a chemical-mechanical polish method. An upper surface of the polysilicon, after partial removal, is at the same level as the upper surface of the interlevel dielectric.
The step of depositing the polish-stop layer comprises depositing a layer of tetraethyl orthosilicate or nitride using chemical-vapor deposition. The step of forming a second gate dielectric layer comprises thermally oxidizing the second semiconductor substrate to a thickness of approximately 15-50 angstroms. The step of depositing a con

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