Elevated source/drain junction metal oxide semiconductor field-e

Details Elevated source/drain junction metal oxide semiconductor field-e Elevated source/drain junction metal oxide semiconductor field-e

1994-09-19

1996-03-05

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 44, 437192, H01L 21265, H01L 2144, H01L 2148

Patent

active

054967503

ABSTRACT:
The described embodiments of the present invention provide a method for fabricating elevated source/drain junction metal oxide semiconductor field-effect transistors. The process does not require the use of selective or epitaxial silicon growth processes. In one embodiment, first a three layer gate stack is formed having a gate dielectric layer (20) beneath a polycrystalline silicon gate layer (22) and a disposable spacer layer (24), such as silicon nitride formed on top of the polycrystalline silicon gate. A conformal dielectric layer is formed overall and anisotropically etched to form sidewall spacers layers (26) on the sides of the gate, and spacer layer stack. The spacer layer (24) is then selectively removed and a layer of amorphous or polycrystalline silicon (30) is deposited overall. A layer of silicon nitride is then deposited on the surface of the polycrystalline silicon layer using chemical-vapor deposition techniques. The silicon nitride layer is etched anisotropically to leave sidewall silicon nitride layers (32) on the portion of the polycrystalline silicon layer over the sidewalls of the gate structure. The exposed layer portion of the polycrystalline silicon layer is then selectively oxidized and a selective silicon nitride etch is then used to remove the sidewall nitride oxidation mask layers, followed by a selective silicon etch to remove the sidewall portion of the polycrystalline silicon layer exposed by the removal of the silicon nitride sidewalls. This leaves elevated source and drain junction regions extending from the sidewalls of the gate on to the field isolation structures surrounding the field-effect transistor area. The silicon layer 40 and 42 extending over the field insulating layer (18) can be patterned and used for local interconnects. The microlithography patterning and silicon dioxide/silicon etch processes for definition of the local interconnect layers can be performed after the selective oxidation process step and prior or after the sidewall nitride and silicon removal.

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