Elevated image sensor array which includes isolation between...

Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Electromagnetic or particle radiation

Reexamination Certificate

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C257S430000, C257S431000, C257S434000, C257S440000, C257S444000

Reexamination Certificate

active

06215164

ABSTRACT:

FIELD OF INVENTION
This invention relates generally to PIN photo diode image sensors. In particular, it relates to an array of elevated PIN diode image sensor in which each diode image sensor is isolated from other diode image sensors, and in which the diode image sensors include a uniquely shaped structure.
BACKGROUND
An array of image sensors or light sensitive sensors detect the intensity of light received by the image sensors. The image sensors typically generate electronic signals that have amplitudes that are proportionate to the intensity of the light received by the image sensors. The image sensors can convert an optical image into a set of electronic signals. The electronic signals may represent intensities of colors of light received by the image sensors. The electronic signals can be conditioned and sampled to allow image processing.
Integration of the image sensors with signal processing circuitry is becoming more important because integration enables miniaturization and simplification of imaging systems. Integration of image sensors along with analog and digital signal processing circuitry allows electronic imaging systems to be low cost, compact and require low power consumption.
Historically, image sensors have predominantly been charged coupled devices (CCDs). CCDs are relatively small and can provide a high-fill factor. However, CCDs are very difficult to integrate with digital and analog circuitry. Further, CCDs dissipate large amounts of power and suffer from image smearing problems.
An alternative to CCD sensors are active pixel sensors. Active pixel sensors can be fabricated using standard CMOS processes. Therefore, active pixel sensors can easily be integrated with digital and analog signal processing circuitry. Further, CMOS circuits dissipate small amounts of power.
FIG. 1
shows a cross-section of a prior art array of image sensors. This array of image sensors includes PIN diode sensors located over a substrate
10
. An interconnection structure
12
electrically connects an N-layer
14
of the PIN diodes to the substrate
10
. An I-layer
16
is formed over the N-layer
14
. A P-layer
18
is formed over the I-layer
16
. The P-layer
18
, the I-layer
16
and the N-layer
14
form the array of PIN diode sensors. A first conductive via
20
electrically connects a first diode sensor to the substrate
10
, and a second conductive via
22
electrically connects a second diode sensor to the substrate
10
. A transparent conductive layer
24
is located over the array of diode sensors. A conductive lead
26
is connected to the transparent conductive layer
24
. The conductive lead
26
is connected to a bias voltage which allows biasing of the P-layer
18
of the array of PIN diode sensors to a selected voltage potential.
A limitation of the image sensor structure of
FIG. 1
is that the individual image sensors are not isolated from each other. That is, light received by a given image sensor will effect neighboring image sensors because current can flow through the N-layer
14
between neighboring image sensors. Charge can flow between the image sensors especially when the light intensity of the received light varies greatly between neighboring image sensors. The P-layer
18
, the I-layer
16
and the N-layer
14
are shared by neighboring image sensors. A trench
28
is formed to provide some isolation between the image sensors by increasing the resistance between the N-layers sections of neighboring image sensors.
Another limitation of the image sensor structure of
FIG. 1
is the electrical connection between the conductive lead
26
and the transparent conductive layer
24
. The transparent conductive layer
24
must be electrically conductive to allow biasing of the PIN diodes, and must be transparent to allow the PIN diodes to receive light. Generally, it is very difficult to bond to the types of materials that must be used to form the transparent conductive layer
24
. Therefore, the conductive lead
26
must be attached to the transparent conductive layer
24
with the aid of some type of clamp or support structure. The result being an electrical connection which is not reliable and which is expensive to produce.
It is desirable to have a plurality of active pixel sensors formed adjacent to a substrate in which the pixel sensors are isolated from each other to reduce coupling between the pixel sensors.
SUMMARY OF THE INVENTION
The invention includes a plurality of image pixel sensors formed adjacent to a substrate. A transparent conductive layer is reliably electrically connected between the image pixel sensors and to a image pixel sensor bias voltage which originates on the substrate. The image pixel sensors are isolated from each other which reduces coupling between the image pixel sensors.
A first embodiment includes an image pixel sensor array. The image pixel sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. A plurality of image pixel sensors are formed adjacent to the interconnect structure. Each image pixel sensor includes a pixel electrode, and an I-layer formed adjacent to the pixel electrode. The I-layer includes a first surface adjacent to the pixel electrode, and a second surface opposite the first surface. The first surface includes a first surface area which is less than a second surface area of the second surface. The image pixel sensor array further includes an insulating material between each image pixel sensor, and a transparent electrode formed over the image pixel sensors. The transparent electrode electrically connects the image pixel sensors and the interconnect structure.
A second embodiment is similar to the first embodiment. Each image pixel sensor of the second embodiment includes a separate P-layer section formed adjacent to the I-layer.
A third embodiment is similar to the first embodiment. Each image pixel sensor of the second embodiment includes a P-layer wherein the P-layer extends adjacently to a plurality of separate I-layers.
A fourth embodiment is similar to the first embodiment. The second embodiment includes the each pixel electrode consisting of an N-layer.
A fifth embodiment is similar to the first embodiment. The third embodiment includes the I-layer sections and the pixel electrodes consisting of amorphous silicon.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


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patent: 5076670 (1991-12-01), Sayyah
patent: 5667597 (1997-09-01), Ishihara
patent: 5834822 (1998-11-01), Hatanaka et al.
patent: 5962844 (1999-10-01), Merrill et al.
patent: 5998794 (1999-12-01), Spivey et al.
patent: 6018187 (2000-01-01), Theil et al.
patent: 405152553 (1993-06-01), None
patent: 360198858 (1993-06-01), None
patent: 405183184 (1993-07-01), None
patent: 405175539 (1993-07-01), None
patent: 405283670 (1993-10-01), None
patent: 406045568 (1994-02-01), None

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