Element placement method and apparatus

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364488, G06F 1750

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active

054652189

ABSTRACT:
An LSI element placement method of placing elements in accordance with an order in which branches are arranged, each branch being constituted by an element array included in a circuit diagram having first and second terminals, the method including a partial circuit extraction step of sequentially extracting data of a predetermined number of branches included in the circuit diagram from the first terminal side of the circuit diagram so as to overlap the data by a predetermined number, and an element placement step of performing an element placement operation based on a genetic algorithm in the extracted partial circuit data, thereby generating an element placement result including placement coordinate data of all elements included in the partial circuit data.

REFERENCES:
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patent: 5225991 (1993-07-01), Dougherty
patent: 5229953 (1993-07-01), Isozaki et al.
patent: 5257201 (1993-10-01), Berman et al.
patent: 5301318 (1994-04-01), Mittal
IEEE Transactions of Computer-Aided Design, vol. CAD-6, No. 6, James P. Cohoon, et al., "Genetic Placement", 1987, pp. 956-964.
IEICE Technical Report, VLD 90-94, Hisashi Sasaki, et al., "A Placement Algorithm for Analog Cell Generation", 1990, pp. 31-38.
Proc. of an Int. Conf. on Genetic Algorithms and their Applications, Michael P. Fourman, "Compaction of Symbolic Layout using Genetic Algorithms", pp. 141-153.

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