Element isolation method for semiconductor devices including etc

Details Element isolation method for semiconductor devices including etc Element isolation method for semiconductor devices including etc

1999-06-29

2000-12-26

Niebling, John F.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438433, 438555, 438704, H01L 2176, H01L 2138, H01L 21302, H01L 21461

Patent

active

061658707

ABSTRACT:
An element isolation method, in particular, a shallow trench isolation (STI) method for semiconductor devices is disclosed in which a trench is formed to have a stepped structure shaped in such a fashion that it has a smaller width at its lower portion than at its upper portion. This stepped trench structure, which includes at least one step, is capable of obtaining an increased metal contact margin, thereby preventing metal contacts from being short-circuited with wells due to a misalignment thereof.

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patent: 5858857 (1999-01-01), Ho
patent: 6001707 (1999-12-01), Liu et al.
patent: 6008129 (1999-12-01), Graff et al.

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