Electrostatic protection structure for MOS circuits

Details Electrostatic protection structure for MOS circuits Electrostatic protection structure for MOS circuits

1997-07-15

1999-10-19

Jackson, Stephen W

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, 361118, 361127, H02H 900

Patent

active

059699230

ABSTRACT:
An ESD protection circuit includes a pair of NPN lateral transistors electrically connected in series with the emitter of one of the transistors electrically connected to the collector of the other transistor. The bases of the two transistors are electrically connected together and are floating. The two transistors may be provided by two MOS transistors having N-type source and drains and P-type channel regions. The channels regions are connected together and are floating.

REFERENCES:
patent: 4419150 (1983-12-01), Soclof
patent: 4656491 (1987-04-01), Igarashi
patent: 5229635 (1993-07-01), Bessolo et al.
patent: 5293057 (1994-03-01), Ho et al.
patent: 5644460 (1997-07-01), Clukey

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