Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2008-05-05
2010-12-28
Nguyen, Danny (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000
Reexamination Certificate
active
07859808
ABSTRACT:
An electrostatic protection circuit, includes a first terminal, a second terminal, a MOS transistor including a gate, a source, and a drain, the gate being coupled to the first terminal, the source being coupled to the second terminal, and an electrostatic protection element connected to the drain, wherein the electrostatic protection element includes a first electrostatic protection element, and a second electrostatic protection element connected between the first terminal and the second terminal. The electrostatic protection circuit is constructed such that a maximum value of a voltage applied to a gate insulating film of the MOS transistor is alleviated to a value equal to or smaller than a desirable value by a current flowing into the first electrostatic protection element at a time of electrostatic application to the first terminal and an internal parasitic resistance of the MOS transistor connected with the second terminal.
REFERENCES:
patent: 6385028 (2002-05-01), Kouno
patent: 6437407 (2002-08-01), Ker et al.
patent: 2005/0231866 (2005-10-01), Mergens et al.
Ajith Amerasekera, “ESD in Silicon Integrated Circuits”, Second Edition, Wiley, 2002, pp. 117-118.
McGinn IP Law Group PLLC
Nguyen Danny
Renesas Electronics Corporation
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