Electrostatic protection circuit

Details Electrostatic protection circuit Electrostatic protection circuit

2008-03-04

2008-03-04

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

11108854

ABSTRACT:
An electrostatic protection circuit to prevent damage to a protected circuit due to electrostatic discharge applied to an input/output terminal, comprises one or more diodes connected in series and provided between a connection point of the input/output terminal and the protected circuit, and a GND terminal and a MOS transistor connected to the diodes in series, and having an operating voltage lower than a signal voltage input from the input/output terminal. The diodes cause a voltage drop in normal operation.

REFERENCES:
patent: 5719737 (1998-02-01), Maloney
patent: 5932918 (1999-08-01), Krakauer
patent: 6556398 (2003-04-01), Chen
patent: 2004/0141270 (2004-07-01), Kaneki
patent: 2005/0213271 (2005-09-01), Chong et al.
patent: 2006/0056121 (2006-03-01), Esmark et al.
patent: 8-222643 (1996-08-01), None
Warrent R. Anderson, et al., “ESD Protection for Mixed-Voltage I/O Using NMOS Transistors Stacked in a Cascode Configuration”, EOS/ESD Symposium 98-54.
Japanese Office Action dated Apr. 18, 2006 and partial English Translation.

Affiliated with

Also associated with

Rating

Electrostatic protection circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrostatic protection circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrostatic protection circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3928491