Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1998-07-27
2001-02-13
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C361S056000
Reexamination Certificate
active
06188263
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an electrostatic protection circuit for use in a semiconductor integrated circuit, such as, an integrated circuit (IC) and a large-scale integrated circuit (LSI).
An electrostatic protection circuit of the type described has been generally used in order to prevent destruction caused by an electrostatic discharge (thereinafter, abbreviated as an ESD) in a semiconductor integrated circuit.
For instance, the conventional electrostatic protection circuit is mainly composed of a P-channel MOS transistor and an N-channel MOS transistor. In this event, these MOS transistors are connected in series to each other. In this condition, the P-channel MOS transistor is connected to a power supply terminal while the N-channel MOS transistor is connected to a ground terminal.
With such a structure, another MOS transistor is often connected to a gate of the above N-channel MOS transistor so as to control a floating state and to reduce a breakdown voltage thereof.
In consequence, the N-channel MOS transistor transfers into a snapback state in order to reduce the EDS pulse which is applied to the gate electrode of the N-channel MOS transistor.
In order to prevent the EDS pulse, the protection transistor must have a large area. Usually, such a protection transistor is structured by a plurality of transistors which are connected in parallel in the electrostatic protection circuit.
However, the breakdown voltages of the protection transistors are fluctuated to one another in the above structure. Consequently, electric charge is concentrated to a specific one of the transistors that has a lowest break down voltage. As a result, the ESD pulse can not be effectively reduced.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide to an electrostatic protection circuit which is capable of preventing fluctuation of breakdown voltages between protection transistors.
It is another object of this invention to provide electrostatic protection circuit which is capable of putting a gate electrode of a protection transistor into a stable floating state when an ESD pulse is applied.
It is still another object of this invention to provide electrostatic protection circuit which is capable of easily transferring into a snap back.
It is still further object of this invention to provide electrostatic protection circuit which is capable of improving resistance to destruction against a protection transistor.
According to this invention, an electrostatic protection circuit protects an internal circuit from electric charge which is applied via an electrode pad. In this event, the electrostatic protection circuit is coupled to a power source.
The above electrostatic protection circuit mainly includes a protection transistor portion, a second transistor and a third transistor.
In this case, the protection transistor portion includes a first transistor having a first gate electrode in order to protect the internal circuit by discharging the electric charge.
Further, the second transistor controls so as to keep the first gate electrode into a floating state before the power source is introduced. Moreover, the third transistor gives a predetermined potential into the first gate electrode.
Consequently, the first gate electrode of the first transistor is raised up to easily put into the floating state. As a result, the breakdown voltage becomes low to easily put into the snapback state. Thereby, the ESD pulse is effectively reduced.
Namely, the third transistor is inserted between the gate electrode of the first transistor and the electrode pad. Thereby, the potential of the first gate electrode of the first transistor is stably increased by the drain and source capacitance of the inserted third transistor when the ESD pulse is applied. Consequently, the first gate electrode is raised up to suppress the fluctuation of the breakdown voltage and to reduce the break down voltage. As a result, the first transistor easily transfers into the snapback state.
REFERENCES:
patent: 5617283 (1997-04-01), Krakauer et al.
patent: 5644459 (1997-07-01), Lien
patent: 5671111 (1997-09-01), Chen
patent: 5729419 (1998-03-01), Lien
patent: 5910874 (1999-06-01), Iniewski et al.
patent: 0 497 471 (1992-08-01), None
patent: 0 687 068 (1995-12-01), None
patent: 62-105462 (1987-05-01), None
Callahan Timothy P.
NEC Corporation
Nguyen Hai L.
Sughrue Mion Zinn Macpeak & Seas, PLLC
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