Electrostatic discharge suppression circuit for integrated circu

Details Electrostatic discharge suppression circuit for integrated circu Electrostatic discharge suppression circuit for integrated circu

1994-12-23

1997-01-28

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, 361111, H02H 900

Patent

active

055983138

ABSTRACT:
An electrostatic discharge suppression circuit is presented for an integrated circuit chip intended for subsequent functioning within a multi-level power supply environment. The suppression circuit includes a clamping circuit, discharge means and a trigger circuit. The clamping circuit shunts an electrostatic discharge at an input and/or output node of the integrated circuit chip to a common node of the suppression circuit. The discharge means is coupled to the common node for dissipating the electrostatic discharge shunted thereto. The trigger circuit is connected to both the common node and the discharge means and includes regenerative feedback for fast turn on of the discharge means as the electrostatic discharge is shunted to the common node such that damage to the integrated circuit chip due to the electrostatic discharge is prevented. An inhibit circuit is coupled to the discharge means for selective inhibiting of the discharge means in response to an inhibit protection signal.

REFERENCES:
patent: 4423431 (1983-12-01), Sasaki
patent: 5208719 (1993-05-01), Wei
patent: 5239440 (1993-08-01), Merrill
patent: 5243490 (1993-09-01), Ontko et al.
patent: 5311391 (1994-05-01), Dungan et al.
patent: 5319259 (1994-06-01), Merrill
patent: 5400202 (1995-03-01), Metz et al.

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