Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2009-06-23
2011-11-08
Nguyen, Danny (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000
Reexamination Certificate
active
08054597
ABSTRACT:
Electrostatic discharge (ESD) structures having a connection to a through wafer via structure and methods of manufacture are provided. The structure includes an electrostatic discharge (ESD) network electrically connected in series to a through wafer via. More specifically, the ESD circuit includes a bond pad and an ESD network located under the bond pad. The ESD circuit further includes a through wafer via structure electrically connected in series directly to the ESD network, and which is also electrically connected to VSS.
REFERENCES:
patent: 5703747 (1997-12-01), Voldman et al.
patent: 5901022 (1999-05-01), Ker
patent: 5973396 (1999-10-01), Farnworth
patent: 6313512 (2001-11-01), Schmitz et al.
patent: 6608363 (2003-08-01), Fazelpour
patent: 6975032 (2005-12-01), Chen et al.
patent: 7265433 (2007-09-01), Pillai et al.
patent: 7335972 (2008-02-01), Chanchani
patent: 7355273 (2008-04-01), Jackson et al.
patent: 2001/0010964 (2001-08-01), Geissler et al.
patent: 2002/0113267 (2002-08-01), Brown et al.
patent: 2004/0195651 (2004-10-01), Zhang et al.
patent: 2004/0238894 (2004-12-01), Furuta
patent: 2005/0266673 (2005-12-01), Hu et al.
patent: 2005/0282381 (2005-12-01), Cohen et al.
patent: 2007/0029646 (2007-02-01), Voldman
patent: 2007/0296055 (2007-12-01), Yen et al.
patent: 2008/0073747 (2008-03-01), Chao et al.
patent: 2008/0254572 (2008-10-01), Leedy
patent: 2009/0283898 (2009-11-01), Janzen et al.
patent: 2010/0244187 (2010-09-01), Voldman
Hsiao et al., “Ultra Low-Capacitance Bond Pad for RF Applications in CMOS Technology”, 2007 IEEE Radio Frequency Integrated Circuits Symposium, pp. 303-306.
Hsiao et al., “Bond Pad Design With Low Capacitance in CMOS Technology for RF Applications”, IEEE Electron Device Letters, vol. 28, No. 1, Jan. 2007, pp. 68-70.
Gebreselasie Ephrem G.
Voldman Steven H.
Canale Anthony
International Business Machines - Corporation
Nguyen Danny
Roberts Mlotkowski Safran & Cole P.C.
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