Electrostatic discharge protective circuit and semiconductor...

Details Electrostatic discharge protective circuit and semiconductor... Electrostatic discharge protective circuit and semiconductor...

2007-08-14

2007-08-14

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

11094091

ABSTRACT:
An electrostatic discharge protective circuit including an ESD protective circuit which has a trigger terminal and forms a discharge path from a first node to a second node when trigger signals are supplied to the trigger terminal, a trigger circuit included in a circuit to be protected which is connected between the first and second nodes, the trigger circuit having a first MOS device, and which functions as a part of the circuit to be protected at the time of normal operation when ESD voltage is not applied, and forms a conductive path between a drain and source of the MOS device when ESD voltage of a predetermined value or more is applied to the first node during a normal operation, and supplying the trigger signals to the trigger terminal of the ESD protective circuit when the first MOS device becomes conductive.

REFERENCES:
patent: 5452171 (1995-09-01), Metz
patent: 6249410 (2001-06-01), Ker
patent: 6580184 (2003-06-01), Song
patent: 7106562 (2006-09-01), Kitagawa
patent: 2002/0053704 (2002-05-01), Avery et al.
patent: 8-293583 (1996-11-01), None
Pending U.S. Appl. No. 10/958,319, filed Oct. 4, 2004.

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