Electrostatic discharge protective circuit

Details Electrostatic discharge protective circuit Electrostatic discharge protective circuit

2002-09-06

2003-03-25

Huynh, Kim (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000, C327S318000

Reexamination Certificate

active

06538868

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an electric circuit. More particularly, the present invention relates to an electrostatic discharge (ESD) protective circuit.
2. Description of Related Art
In the integrated circuit (IC), the electrostatic discharge is the major damage in the process of the dynamic random access memory (DRAM) and the statistic random access memory (SRAM) or after complete the wafer process. Therefore, an electrostatic discharge protective circuit usually is designed on the circuit and avoids the electrostatic from outside medium. For example, the human body walks on the carpet and carries approximately few hundreds or thousands electrostatic voltage in the status of higher relativity humidity (RH). However, the human body also carries approximately over ten thousands volt of the electrostatic voltage in the status of lower relativity humidity. When those electrified body touches the wafer and the wafer is losing its efficiency by the electrostatic discharge. Nowadays, the electrostatic discharge is the most serious problem in the fabrication of the complementary metaloxide semiconductor (CMOS).
Therefore, there are various kind method that is designed to avoid the wafer damage by the electrostatic discharging. The most common conventional method is utilizing the hardware to avoid the electrostatic discharging, which is designed and protected the internal circuit on an electrostatic discharge protective circuit between the internal circuit and every bonding pad. Currently, the electrostatic discharge problem is the most malfunction cases on the deep sub-micro, or on the even smaller integrated circuit. Therefore, a method for improving the efficiency of the electrostatic discharge protective circuit is greatly intended by the manufacturers.
FIG.
1
through
FIG. 3
show three conventional designs of the electrostatic discharge protective circuit. Referring to
FIG. 1
, the electrostatic discharge protective circuit, which is used in an overvoltage tolerant output buffer, connects in series with a P-type metal-oxide semiconductor (PMOS) transistor
42
, two N-type metal-oxide semiconductor (NMOS) transistors
44
and
46
. The drain regions of the NMOS transistor
44
and the PMOS transistor
42
are connected to a bonding pad
52
. A source region of the PMOS transistor
42
connects to a system power source. A source region of the NMOS transistor
46
connects to a grounded node. The gates of the PMOS transistor
42
and the NMOS transistor
46
can receive the output of a pre-stage driver
50
. Therefore, the gate of the NMOS transistor
46
is turned on. Also, and the gate of NMOS transistor
44
connects to the system power source, wherein since the gate of NMOS transistor
44
is connected to the system power source, it can maintain a stable voltage to avoid a high voltage on the NMOS transistor
46
. For example, a 5 volts voltage can cause an issue of poor reliability. The bonding pad
52
can be connected to a signal with a voltage greater than Vcc. The NMOS transistor
46
is usually operated at 3.3 volts.
FIG. 1
shows a circuit design using an output buffer as the electrostatic discharge protective circuit, which is used in an overvoltage tolerant output buffer.
FIG. 2
shows the conventional design of the electrostatic discharge protective circuit. It is a similar design as like
FIG. 1
, but used in an overvoltage tolerant input buffer. Here, a gate electrode of the PMOS transistor
42
is connected to a well control circuit, and gate electrode of the NMOS transistor
46
connects to the grounded node.
Moreover,
FIG. 3
shows the electrostatic discharge protective circuit used in a conventional non-overvoltage tolerant input buffer, where the design includes two sets of protective circuit, and connected in parallel. Because effects of the parasitic capacitance
60
and diode of the MOS transistor, it also can conduct the electrostatic charges to the grounded node or the power source. In the foregoing description of the conventional design of the electrostatic discharge protective circuit, all the protective ability is either insufficient or not being used in the overvoltage tolerant input/output buffer.
SUMMARY OF THE INVENTION
The invention provides electrostatic discharge protective circuit, that includes a first PMOS transistor, a first NMOS transistor and a second NMOS transistor and they all connect in series. More particularly, the first PMOS transistor of a source region connects to a system power source, and a drain region connects to a conductive pad, and a gate receives output of the pre-stage driver, and the base is connected to the well control circuit. A gate of the first NMOS transistor connects to a first node A. A gate of the second NMOS transistor connects to a third node C, and one source region connects to a grounded node. The third node C also can receive output of the pre-stage driver. There is a first resistor in between the first node A and the system power source. There is a second PMOS transistor in between the first node A and the third node C. The source region connects to the node A and the drain regions connects to node C., and the substrate of the second PMOS transistor also connects to the first node A. Moreover, a gate of the second PMOS transistor connects to a second node B. There is a second resistor that connected between the second node B and the system power source, and there is a capacitor that connects between the second node B and the grounded node.
In the foregoing descriptions, when an electrostatic pulse enters through the conductive pad, because the second NMOS transistor has the equivalence capacitor, the voltage of the first node A rises. Also and, because the capacitor exists between the second node B and the grounded node, and the second node B voltage is equal to zero. Then the voltage of the third node C rises up, because the second PMOS transistor is turned on. As a result, the electrostatic pulse entering from the conductive pad can lead the electrostatic pulse to the grounded node through the first and the second NMOS transistors connected in series.
The invention also provides an electrostatic protective circuit. It can protect an internal circuit, comprising a first P-type metal-oxide semiconductor (PMOS) transistor, a first N-type metal-oxide semiconductor (NMOS) transistor, and a second NMOS transistor and they all connected in series. More particularly the first PMOS transistor of a source region, a gate electrode, and a drain regionrespectively connect to a system power source, a well control circuit, and a conductive pad, and the conductive pad is connected to the input buffer
58
. A gate of the first NMOS transistor connects to the first node A. A gate of the second NMOS transistor connects to a third node C. Source/drain regions of the second NMOS transistor respectively connects to a grounded node and the third node C. Also it includes a first resistor that connected between the first node A and the system power source. A second PMOS transistor is connected between the first node A and the third node C, where a substrate of the second PMOS transistor is also connected to the first node A, and a gate of the second PMOS transistor is connected to a second node B. A second resistor connects in between the second mode B and the system power source. A capacitor is connected between the second node B and the grounded node. A third NMOS transistor has a gate electrode, a source region, a drain region, respectively connected to the third node C, the grounded node, and the second node B.
In the foregoing, when an electrostatic pulse entries from the conductive pad, because the second NMOS transistor has the equivalent capacitor, the voltage of the first node A rises up. Also and, because the capacitor connected between the second node B and the grounded node and the voltage of second node B is equal to zero. Therefore the second PMOS transistor between the first node A and the third node C is turned on. Then, the third node C voltage rises up

Affiliated with

Also associated with

Rating

Electrostatic discharge protective circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrostatic discharge protective circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrostatic discharge protective circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3074820