Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Device protection
Reexamination Certificate
2001-02-13
2003-09-02
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Device protection
C438S621000, C257S174000, C257S355000, C257S364000, C257S362000, C361S111000, C361S056000, C361S091200
Reexamination Certificate
active
06614061
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a semiconductor device. In particular, the present invention relates to an electrostatic discharge-protection semiconductor device to prevent the device comprising field-oxide devices and silicon-controlled rectifiers (SCR) from damage.
2. Description of the Related Art
Electrostatic discharges, ESD hereinafter, is a common phenomenon that occurs during the handling of semiconductor integrated circuit, IC hereinafter, devices. Electrostatic charges may accumulate and cause potentially destructive effects on an IC device. ESD stressing typically can occur during a testing phase of IC fabrication, during installing of the IC onto a circuit board, as well as during use of equipment into which the IC has been installed. Damage to a signal IC due to poor ESD protection in an electronic device can partially or sometimes completely disrupt its operation.
There are several ESD stress models based on the reproduction of typical discharge pulses to which the IC may be exposed during manufacturing or handling. Three standard models, known as the Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM) have been proposed. The Human Body Model is set forth in U.S. Military Standard MIL-STD-883, Method 3015.6. The military standard models the electrostatic stress produced on an IC device when a human carrying an electrostatic charge touches the lead pins of the IC device. The machine model is set forth in Industry Standard EIAJ-IC-121, which describes the electrostatic stress produced on an IC device when a machine carrying electric charges contacts the lead pins of the IC device. The charged device model describes the ESD current generated when an IC already carrying electric charges is grounded while being handled.
Refer to FIG.
1
.
FIG. 1
shows the top view of the traditional structure of an electrostatic discharge-protection semiconductor device.
As shown in
FIG. 1
, the traditional anti-electrostatic semiconductor device comprises a P-type substrate
11
comprising an N-type well
12
. The P-type substrate
11
further comprises a P-type doped region
13
and an N-type doped region
14
which are connected to a specific voltage point
18
, wherein the specific voltage point
18
supplies the ground voltage or the Vss voltage. In the N-type well
12
, there is a P-type doped region
15
and an N-type doped region
16
, which are connected to a pad
19
, respectively. Moreover, there is an N-type doped region
17
connected to the pad
19
on the P-type substrate
11
.
Refer to
FIG. 2
,
FIG. 2
shows a cross-sectional view along the line A-A′ in
FIG. 1. A
PNP bipolar junction transistor is composed of the P-type doped region
15
, the N-type well
12
and the P-type substrate
11
, which act as the emitter, the base, and the collector of the PNP bipolar junction transistor, respectively. In addition, An NPN bipolar junction transistor is composed of the N-type well
12
, the P-type substrate
11
, and the N-type doped region
14
, which are used as the collector, the base, and the emitter of the NPN bipolar junction transistor, respectively. The N-type doped region
14
and the P-type doped region
15
are connected to the pad
19
, and the N-type region
14
and the P-type region
13
are connected to Vss
18
. Therefore, the PNP bipolar junction transistor and the NPN bipolar junction transistor are combined to form a silicon-controlled rectifier, SCR hereinafter.
Refer to
FIG. 3
,
FIG. 3
shows a cross-sectional view along the line B-B′ in FIG.
1
. In
FIG. 3
, a field-oxide device is composed of the N-type doped region
17
, the P-type substrate
11
, and the N-type doped region
14
. The N-type doped region
17
(collector) is connected to the pad
19
and the N-type doped region
14
(emitter) is connected to the Vss. Further, field-oxide layer of the field-oxide device is made by Local oxidation of silicon technology, LOCOS hereinafter.
FIG. 4
is an equivalent circuit diagram of the semiconductor in FIG.
1
. When the voltage difference between the pad
19
and the Vss reaches to a specific degree caused by the charge accumulating, at this time, the field-oxide device
42
will turn on then provide enough current to cause the silicon-controlled rectifier
41
turn on immediately. Hence, the turn on voltage of the silicon-controlled rectifier
41
will decrease. Therefore, the combining of the silicon-controlled rectifier
41
and the field-oxide device
42
will be lower than the turn on voltage of the silicon-controlled rectifier
41
than using the silicon-controlled rectifier
41
alone. When the silicon-controlled rectifier
41
is turned on, the charge accumulating in the semiconductor device will flow to the ground. Thus, the technology prevents the elements of the semiconductor device from damaging by the electrostatic stress.
Refer to
FIG. 3
, which shows the appearance of the field-oxide layer
31
in the field-oxide device
42
. Because the field-oxide layer
31
is made by the LOCOS, there is a smooth “bird's beak structure” in the field-oxide layer
31
. Therefore, the charge accumulating in the N-type doped region
17
will pass through the field-oxide layer
31
easily. However, although the bird's beak structure may ease the flowing of the charges, but the bird's beak structure takes a lot of space and will decrease the integration of the semiconductor structure designs.
Therefore, for solving the problem of wasted space caused by the bird's beak structure, the conventional technology develops a Shallow Trench Isolation method to forming the field-oxide layer
31
. The Shallow Trench Isolation method comprises the steps as follows. First, etches a trench on the field-oxide layer
31
, then deposits a silicide on the trench directly. Therefore, a field-oxide layer is formed without the bird's beak structure. Hence, the integration of a semiconductor device will increase.
However, although forming the field-oxide layer by the shallow trench isolation method will decrease the size of the field-oxide layer, but it is difficult for the charges to pass through the field-oxide layer by the shallow trench isolation because of the resistance between the field-oxide layer
31
and the N-type doped region. Therefore, when a great deal of electrostatic stress in the semiconductor device, overheating will be generated in the region between the collector of the field-oxide device and the field-oxide layer, which will cause the field-oxide devices to be broken.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an electrostatic discharge-protection device, which combines the silicon-controlled rectifier and the field-oxide device to make the silicon-controlled rectifier turn on at the lower voltage. Moreover, in order to improve the integration of the semiconductor device, the field-oxide layer of the field-oxide device according to the present invention is formed by the shallow trench isolation method. Then, to prevent the field-oxide device from forming by the shallow trench isolation method and breaking because of the overheating, the present invention provides a well structure in the field-oxide device. It is because the area of the well structure is large, so the well structure has good performance in radiating the heat. Moreover, this well structure with a relatively larger area may prevent the field-oxide device from failing because of the high temperature. When the field-oxide device drives the silicon-controlled rectifier successfully, the element of the semiconductor device will not be broken by the electrostatic stress.
To achieve the above-mentioned object, the present invention provides an electrostatic discharge-protection device located between a pad and a specific voltage point. The electrostatic discharge-protection device has a P-type substrate. Then a first N-type well, a first P-type doped region, and a first N-type doped region, are formed on the P-type substrat
Berry Renee R
Ho Hoai
Ladas & Parry
Windbond Electronics Corp.
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