Electrostatic discharge protection scheme in low potential...

Details Electrostatic discharge protection scheme in low potential... Electrostatic discharge protection scheme in low potential...

2001-01-24

2003-09-23

Huynh, Kim (Department: 2182)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000

Reexamination Certificate

active

06624998

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to the control and attenuation of electrostatic discharge (ESD) to prevent damage to integrated circuits (IC). The invention enables isolation of ICs from voltage drops caused by ESD current. More specifically, the invention implements a divided rail concept to strategically direct undesirable ESD current away from sensitive circuitry.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) normally require a special electrostatic discharge (ESD) protection circuit for all pads. ESD is a discharge of static electricity that can destroy sensitive electronic devices and circuitry unless major steps are taken to prevent its occurrence. ESDs are generally stored on non-conductive surfaces and dielectric components of IC devices. Both discreet semi-conductor devices and integrated circuits may be damaged by ESD. Specifically, as ICs have achieved a higher speed, smaller geometries, lower power and lower voltage, they have become more susceptible to ESD damage.
Prior art ESD protection circuit systems include special low impedance elements such as, for example, forward biased diodes or snap back devices that route the ESD current to one of two power supply rails, depending upon the polarity of the ESD pulse. In these systems, typically, the ESD current is directed through a power supply rail to complete the ESD discharge circuits. For normal operation of an IC, the voltage, at any point along a metal rail, is the same as any other point within a difference of a few millivolts. However, during an ESD episode, the interconnect conducts a large ESD current. This may include sizeable and potentially destructive voltage drops along the interconnect because of the large ESD current flowing through the resistance of the metal rail.
Regarding the prior art, ESD protection circuits operate under a high voltage potential and would cause irreversible damage if used in small potential circuits. For example, U.S. Pat. No. 4,692,834 to Iwashi et al, discloses an electrostatic discharge protection circuit with variable limiting thresholds for MOS device. Specifically, the invention relates to the protection from over voltage damage, a MOS input device which is to be responsive to a high voltage input signal. The invention implements a variable limiting threshold for an input signal as part of the electrostatic discharge protection circuit. Specifically, the invention utilizes a gate controlled diode utilizing a gate controlled drain avalanche breakdown. In this embodiment, a preselected potential is continuously or optionally applied to the gates of the gate controlled diode from the exterior or interior of the integrated circuit, so that the potential limiting threshold for the input signal is enhanced. Thereafter, a high voltage input signal for the MOS input semiconductor integrated circuit is free from potential limiting operation and the integrated circuit can receive the information of the high voltage input signal.
Further, U.S. Pat. No. 5,237,395 to Lee, discloses a power rail ESD protection circuit. Specifically, first and second current shunt passes between the power rails are maintained non-conductive during normal circuit operation, and are triggered to a conductive mode in response to an ESD event on the power rail. A triggering circuit may employ a logic gate such as an inverter, with its input coupled to the positive power rail that maintains a low level output during normal operation and provides a high output in response to an ESD event on the power rail.
U.S. Pat. No. 5,287,241 to Puar, discloses a shunt circuit for electrostatic discharge protection. Specifically, the invention discloses a circuit that is added to a complementary metal oxide silicone (CMOS) integrated circuit (IC) to provide an intentional non-reversed biased V
dd
to V
ss
shunt pass for transient currents such as electrostatic discharges. The circuit protects the IC from ESD damage by turning on before any other pass, thus directing the ESD transient current away from easily damaged structures. More specifically, the ESD transient current is steered from the VVD rail to the V
ss
rail through the on conduction of a P-channel transistor whose source and drain are connected to V
dd
and V
ss
respectively. The voltage on the gate of this transistor follows the V
dd
supply rail because it is driven by a delay network formed by a second transistor in a capacitor. This V
dd
tracking delay network turns the V
dd
to V
ss
transistor on during a transient and off during normal operation of the IC.
U.S. Pat. No. 5,473,500 to Payne et al, relates to electrostatic discharge circuits for high speed, high voltage circuitry. Specifically, the invention relates to a protection circuit which includes a first controlled path for discharging negative ESD pulses introduced at the signal node. The first controlled path is from the signal node to V
cc
via the source and drain electrodes of a first transistor. The gate of the transistor is at a soft ground by connection of the gate through a resistor and an inverter to a fixed voltage supply potential (V
cc
). A second controlled path discharges positive ESD pulses via source and drain regions of serially connected second and third transistors to ground. The second transistor has a ate tied at V
cc
by means of a resistor and inverter to ground. The third transistor is at soft ground by means of a resistor and inverter to V
cc
. The third transistor is turned on by a positive voltage exceeding the threshold voltage of the third transistor. The protection circuit may include a third controlled path through a fourth transistor, if low voltage circuitry is tied to the signal node. The fourth transistor includes a gate that is tied high by connection of the gate to ground via transistor and inverter.
U.S. Pat. No. 5,530,612 to Maloney, relates to electrostatic discharge protection circuits using biased and terminated PNP transistor chains. Specifically, the disclosure relates to a bias network that is used to augment the diode string to distribute small but significant forward current to the diodes. Also disclosed is the use of cantilever diodes which provide PNP Darlington gain block for ESD protection rather than for amplifying signals in bipolar ICs. In one disclosure, the termination is the principal element of device novelty and that which makes the protection device “stand-alone”. The termination supplies final base current to the gain block for a limited amount of time, so that ESD charge can be shunted harmlessly through the PNP chain, but assures that the structure draws no current from a stable power supply long term. The entire structure is able to absorb noise spikes as well as ESD pulses. The termination also makes provisions for discharging its capacitor between ESD pulses, as is necessary for standardized testing. The invention is specifically suited for an IC power supply clamp, and reduces the damage often seen on IC C power supplies during extensive ESD testing.
U.S. Pat. No. 5,584,870 to Single et al, describes an implant ESD protection network. Specifically, the invention relates to a protective component that is provided for protecting a cochlear implant from external electrostatic discharges. The implant receives signals through a receiver coil inductively coupled to a transmitter coil. The protective component is disposed across the coil of the transmitter.
U.S. Pat. No. 5,644,460 to Clukey, discloses a multi-rail electrostatic discharge protection device. The invention relates to a device for protecting against circuit damaging voltage spikes at input nodes and output nodes of electrical circuits and between high and low potential power rails. The voltage spikes are of the type identified generally as electrostatic discharges. The device includes a plurality of semiconductor elements which are preferably bipolar transistors, coupled to the power rails and an input node or an output node of the circuit such that all types of electrostatic discharges can be diverted using the single device of the pr

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