Electrostatic discharge protection in a semiconductor device

Details Electrostatic discharge protection in a semiconductor device Electrostatic discharge protection in a semiconductor device

2004-10-29

2009-02-24

Jackson, Stephen W (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

07495873

ABSTRACT:
An ESD protection circuit for protecting a circuit from an ESD event occurring between a first voltage supply node and a second voltage supply node associated with the circuit to be protected includes an MOS device having a gate terminal, a first source/drain terminal and a second source/drain terminal. The first source/drain terminal is connected to the first voltage supply node and the second source/drain terminal is connected to the second voltage supply node. The ESD protection circuit further includes a trigger circuit coupled to the gate terminal of the MOS device. The trigger circuit is configured to generate a control signal at the gate terminal of the MOS device for activating the MOS device during the ESD event. At least a portion of the trigger circuit is formed in a floating well which becomes biased to a voltage that is substantially equal to a first voltage when the first voltage is supplied to the first voltage supply node or to a second voltage when the second voltage is applied to the second voltage supply node, whichever voltage is greater.

REFERENCES:
patent: 4656493 (1987-04-01), Adler et al.
patent: 5239440 (1993-08-01), Merrill
patent: 5559659 (1996-09-01), Strauss
patent: 5594381 (1997-01-01), Bingham
patent: 5610791 (1997-03-01), Voldman
patent: 5767733 (1998-06-01), Grugett
patent: 5929667 (1999-07-01), Abadeer et al.
patent: 5969541 (1999-10-01), Waggoner
patent: 6404270 (2002-06-01), Meng
patent: 6757147 (2004-06-01), Tong et al.
patent: 6927957 (2005-08-01), Bakulin et al.
patent: 6965263 (2005-11-01), Bringivijayaraghavan
patent: 2002/0085328 (2002-07-01), Liu et al.
patent: 2004/0125521 (2004-07-01), Salling et al.
patent: 2004/0263238 (2004-12-01), Thorp et al.
patent: 2005/0083623 (2005-04-01), Yeh et al.
R. Merrill et al., “ESD Design Methodology,” Electrical Overstress/Electrostatic Discharge Symposium Proceedings, pp. 5B.5.1-5B.5.5, Sep. 1993.

Affiliated with

Also associated with

Rating

Electrostatic discharge protection in a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrostatic discharge protection in a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrostatic discharge protection in a semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4055324