Electrostatic discharge protection for CMOS integrated circuits

Details Electrostatic discharge protection for CMOS integrated circuits Electrostatic discharge protection for CMOS integrated circuits

1991-08-21

1994-04-05

DeBoer, Todd

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

361111, 361 56, 257356, H02H 904

Patent

active

053010841

ABSTRACT:
An electrostatic discharge ("ESD") protection circuit for use in CMOS I.C. devices provides a low voltage path to and from each input and output ("I/O") pad and power pad by using the wide, low resistance metal VCC and Vss rings and parasitic bipolar transistors configured as three terminal devices at each I/O and power pad. The present invention also provides a clamp, between the VCC and VSS rings, capable of being rapidly switched into the conducting state during an ESD event so as to shunt excess bias current that could otherwise damage reverse biased junctions during an ESD event.

REFERENCES:
patent: 4423431 (1983-12-01), Sasaki
patent: 4819047 (1989-04-01), Gilfeather et al.
patent: 4930036 (1990-05-01), Sitch
patent: 4962320 (1990-10-01), Okada et al.
patent: 4990802 (1991-02-01), Smooha
Dialog Information Services, Inc. search of 25 Apr. 1991.

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