Electrostatic discharge protection for a circuit capable of...

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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Reexamination Certificate

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07626790

ABSTRACT:
An electrostatic discharge protection circuit includes a first NMOS transistor and a second NMOS transistor cascode-connected between a high-voltage supply terminal (VDD) and an input pad (PAD), a third NMOS transistor and a fourth NMOS transistor cascode-connected between PAD and a low-voltage supply terminal (VSS), a first capacitor connected between VDD and a node VT that is connected to gate terminals of the second NMOS transistor and the third NMOS transistor, a second capacitor connected between the node VT and PAD, and a diode connected between VDD and the node VT.

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patent: 7477498 (2009-01-01), Huebl
patent: 2007/0058306 (2007-03-01), Poulton
patent: 2007/0103825 (2007-05-01), Ker et al.
patent: 2007/0253128 (2007-11-01), Tiebout et al.

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