Semiconductor device manufacturing: process – Making regenerative-type switching device
Reexamination Certificate
1999-08-23
2002-01-15
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making regenerative-type switching device
C257S173000, C257S355000, C257S360000, C257S362000, C361S056000, C361S111000, C361S117000, C361S118000, C361S212000
Reexamination Certificate
active
06338986
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrostatic discharge protection device used in a semiconductor integrated circuit for protecting the semiconductor integrated circuit from breaking due to an electrostatic charge flowing into or out of the circuit (electrostatic discharge phenomenon). The present invention also relates to a method for producing such an electrostatic discharge protection device, and an electrostatic discharge protection circuit using the same.
2. Description of the Related Art
The electrostatic discharge, as discussed in the field of semiconductor integrated circuits, is a phenomenon in which an electrostatic charge flows into a semiconductor integrated circuit from an electrostatically charged person or machine, or an electrostatic charge flows into an external conductor from a semiconductor integrated circuit which has been electrostatically charged by friction, etc. When the electrostatic discharge phenomenon occurs, an amount of electrostatic charge flows into or out of a semiconductor integrated circuit in a moment. Thus, an excessive current flows through the semiconductor integrated circuit device, whereby an excessive voltage flows through an internal circuit. Consequently, junction breakdown, line melting, oxide film dielectric breakdown, or the like, may occur, thereby breaking the semiconductor integrated circuit.
In order to prevent the semiconductor integrated circuit from breaking due to the electrostatic discharge phenomenon, an electrostatic discharge protection device is commonly provided between an external terminal and an internal circuit of a semiconductor integrated circuit so as to form a bypass circuit for static electricity. Such an electrostatic discharge protection device is provided during a step in the production of the semiconductor integrated circuit. In order not to increase the production cost of a semiconductor integrated circuit, it is desirable to provide the electrostatic discharge protection device without performing any additional step.
Commonly-employed electrostatic discharge protection devices include current limiting elements for limiting a transient current flowing in a semiconductor integrated circuit, such as a diffused resistor, and a polysilicon resistor. Other such protection circuits include a voltage clamping element for suppressing the voltage applied to an internal circuit, such as a diode, a thyristor, a MOS transistor, and a bipolar transistor.
A thyristor, as a current clamping element, can advantageously produce an excessive discharge current. However, a trigger voltage at which the thyristor is turned ON is generally high, e.g., about 25 V to about 40 V, whereby the semiconductor integrated circuit may break before the thyristor is activated. In view of this, thyristors have been adjusted to reduce the trigger voltage.
FIG. 24
is a cross-sectional view illustrating an exemplary conventional electrostatic discharge protection device, and more particularly, a thyristor that can be triggered by a low voltage (Japanese Patent No. 2505652).
Referring to
FIG. 24
, an n-type well
2
is provided in a p-type substrate
1
as an n-type impurity diffused layer. A p-type anode high impurity concentration region
4
and an n-type anode gate high impurity concentration region
5
are provided in the n-type well
2
. A p-type high impurity concentration region
55
is provided across the boundary between the n-type well
2
and the p-type substrate
1
, so that a portion of the p-type high impurity concentration region
55
is surrounded by the n-type well
2
and another portion thereof is surrounded by the p-type substrate
1
. An n-type cathode high impurity concentration region
6
and a p-type cathode gate high impurity concentration region
7
are provided in another region of the p-type substrate
1
away from the n-type well
2
. The p-type anode high impurity concentration region
4
and the n-type anode gate high impurity concentration region
5
are connected to an anode terminal
36
via a contact
16
and a metal
18
. The n-type cathode high impurity concentration region
6
and the p-type cathode gate high impurity concentration region
7
are connected to a cathode terminal
54
via another contact
16
and another metal
53
.
Referring to
FIG. 25
, the low voltage thyristor as illustrated in
FIG. 24
may be provided between a power supply line
52
and a reference voltage line
45
of a semiconductor integrated circuit. An anode terminal
36
of the electrostatic discharge protection device
56
is connected to the power supply line
52
, and the cathode terminal
54
of the electrostatic discharge protection device
56
is connected to the reference voltage line
45
. An excessive voltage due to an electrostatic discharge is applied to the power supply line
52
. When the electrostatic discharge reaches the trigger voltage of the thyristor provided in the electrostatic discharge protection device
56
, the thyristor is turned ON, thereby forming a low-resistance path between the power supply line
52
and the reference voltage line
45
. The low-resistance path bypasses an electrostatic charge flowing into the device from a power supply terminal
51
to a reference voltage terminal
44
, thereby preventing breakdown of a semiconductor integrated circuit
57
connected to the power supply line
52
and the reference voltage line
45
.
Where the p-type high impurity concentration region
55
is not provided, the trigger voltage of the thyristor is determined by the breakdown voltage between the p-type substrate
1
and the n-type well
2
. With the production process of a common CMOS semiconductor integrated circuit, the trigger voltage will be as high as about 25 V to about 40 V. With such a high voltage, internal circuits of the semiconductor integrated circuit
57
will break down before the thyristor is turned ON. The trigger voltage of the thyristor illustrated in
FIG. 24
is determined by the breakdown voltage between the p-type high impurity concentration region
55
and the n-type well
2
. Due to the presence of the p-type high impurity concentration region
55
, the breakdown voltage can be reduced below the breakdown voltage between the p-type substrate
1
and the n-type well
2
.
Since the minimum process dimension of a semiconductor integrated circuit became minute, and a demand for a faster operation of an integrated circuit increased, a salicide (self-alignment silicide) step has been employed in order to reduce the source/drain diffused resistance or the gate line resistance of a MOS transistor. In the salicide step, a silicon substrate surface and a polysilicon surface, whose resistances are to be reduced, are first adjusted to be exposed, on which a high melting point metal such as titanium or cobalt is deposited. Then, a heat treatment is performed so as to provide an alloy (silicide) of silicon and the high melting point metal.
In the salicide step in the CMOS process, a silicide layer is provided on a portion of a silicon surface which is not covered with a gate oxide film or a device separation insulator of the MOS transistor. In the thyristor of
FIG. 24
, which can be triggered by a low voltage, the silicon surfaces of the p-type high impurity concentration region
55
(to be the trigger) and then-type well
2
are both covered with the silicide layer. Then, the p-type high impurity concentration region
55
and the n-type well
2
are shortcircuitted with each other, whereby breakdown can no longer occur therebetween. Due to the shortcircuit, the n-type anode gate high impurity concentration region
5
, then-type well
2
, the p-type high impurity concentration region
55
, the p-type substrate
1
, and the p-type cathode gate high impurity concentration region
7
are shortcircuitted with one another, whereby the anode terminal
36
and the cathode terminal
54
are shortcircuitted with each other.
A way of avoiding the shortcircuit between the p-type high impurity concentration region
55
and the n-type well
2
Aoki Eiji
Fujii Katsumasa
Hsu Sheng Teng
Kawazoe Hidechika
Elms Richard
Luu Pho
NIxon & Vanderhye P.C.
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