Electrostatic discharge protection device for CMOS integrated ci

Details Electrostatic discharge protection device for CMOS integrated ci Electrostatic discharge protection device for CMOS integrated ci

1985-09-27

1988-03-29

Edlow, Martin H.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 231, 357 2312, 357 2313, 357 42, 357 13, 307304, H01L 2978

Patent

active

047347520

ABSTRACT:
An integrated circuit device for protecting the circuitry of an integrated circuit from an electrostatic discharge into an output pin of the chip is disclosed. In a preferred embodiment, the device comprises an n-well, n-channel, polysilicon-gated FET structure, which operates in a punch-through mode, coupled to an output pad and an output buffer of the circuit. Back biasing in the chip system affords additional inhibition to turn-on during normal system operation.

REFERENCES:
patent: 4342045 (1982-07-01), Kim

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