Electrostatic discharge protection device

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device

Reexamination Certificate

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Details

C257S122000, C257S141000, C257S162000, C257S173000, C257S175000, C257S353000, C257S355000, C257SE29225

Reexamination Certificate

active

07667241

ABSTRACT:
An electrostatic discharge protection device for protecting a node includes a transistor, a silicon controlled rectifier, a second contact region laterally displaced from the first contact region, and a collection region adjacent the source region. The transistor includes a semiconductor substrate, a source region, a channel region adjacent the source region, a gate over the channel region, and a drain region laterally displaced from the channel. The silicon controlled rectifier includes the source region, a portion of the substrate, a doped well, and a first contact region in the well, laterally displaced from the drain region. The collection region, the source region and the gate, are metallically connected. The node, the first contact region, and the second contact region, are metallically connected, and the drain region is not metallically connected to the node.

REFERENCES:
patent: 5182220 (1993-01-01), Ker et al.
patent: 5719733 (1998-02-01), Wei et al.
patent: 5754380 (1998-05-01), Ker et al.
patent: 5825600 (1998-10-01), Watt
patent: 6086879 (2000-07-01), Mowbray et al.
patent: 6169309 (2001-01-01), Teggatz et al.
patent: 6365940 (2002-04-01), Duvvury et al.
patent: 6433368 (2002-08-01), Vashchenko et al.
patent: 6548874 (2003-04-01), Efland et al.
patent: 6576934 (2003-06-01), Cheng et al.
patent: 6639284 (2003-10-01), Chatterjee et al.
patent: 6696708 (2004-02-01), Hou et al.
patent: 6924531 (2005-08-01), Chen et al.
patent: 2002/0081783 (2002-06-01), Lee et al.
patent: 2004/0004231 (2004-01-01), Peng et al.
patent: 2004/0033666 (2004-02-01), Williams et al.
patent: 2005/0151160 (2005-07-01), Salcedo et al.
patent: 2005/0174142 (2005-08-01), Jeon et al.
patent: 2005/0254189 (2005-11-01), Wu et al.
patent: 2006/0006462 (2006-01-01), Chang et al.
patent: 2006/0274465 (2006-12-01), Wu et al.
A.J. Walter, S.T. Ward and H. Puchner “Novel Robust High Voltage ESD Clamps for LDMOS Protection”, Cypress Semiconductor, IEEE 07CH37867 45thAnnual International Reliability Physics Symposiums, 2007.
Chung, Y. et al., “Snapback breakdown dynamics and ESD susceptibility of LDMOS”, 44thAnnual International Reliability Physics Symposium, San Jose, pp. 352-355, (2006).
Duvvury, C. et al., “Efficient NPN operation in high voltage NMOSFET for ESD robustness”, IEDM, pp. 345-348, (1995).
Duvvury, C. et al., “Lateral DMOS design for ESD robustness”, IEDM, pp. 375-378, (1997).
Duvvury, C. et al., “Device integration for ESD robustness of high voltage power MOSFETs”, IEDM, pp. 407-410, (1994).
Encyclopedia of Chemical Technology, Kirk-Othmer, vol. 14, pp. 677-709, (1995).
Kawamoto, K. et al., “A no-snapback LDMOSFET with automotive ESD endurance”, IEEE Transactions on Electron Devices, vol. 49, No. 11, pp. 2047-2053, (2002).
Lee, J-H. et al., “Novel ESD protection structure with embedded SCR LDMOS for smart power technology”, 40thAnnual International Reliability Physics Symposium, Dallas, Texas, pp. 156-161, (2002).
Mergens, M.P.J. et al., “Analysis of lateral DMOS power devices under ESD stress conditions”, IEEE Transactions on Electron Devices, vol. 47, No. 11, pp. 2128-2137, (2000).
USPTO Final Rejection for 11/234,255, dated Jan. 8, 2009, 10 pages.
USPTO Non-Final Rejection for 11/234,255, dated Mar. 4, 2008, 10 pages.
USPTO Non-Final Rejection for 11/234,255, dated Aug. 27, 2007, 12 pages.
Utility Application of Specifications for 11/234,255, dated Sep. 23, 2005, 22 pages.
Utility Application of Claims for 11/234,255, dated Sep. 23, 2005, 5 pages.
Utility Application of Abstract for 11/234,255, dated Sep. 23, 2005, 1 page.
Utility Application of Drawings for 11/234,255, dated Sep. 23, 2005, 2 pages.
USPTO Final Rejection for U.S. Appl. No. 11/234,255 (PM05025) dated Apr. 23, 2009; 14 pages.
USPTO Requirement for Restriction/Election for U.S. Appl. No. 11/234,255 (PM05025) dated Sep. 3, 2008; 7 pages.
USPTO Requirement for Restriction/Election for U.S. Appl. No. 11/234,255 (PM05025) dated Jul. 5, 2007; 6 pages.
Walker et al., “Novel Robust ESD Clamps for LDMOS Protection,” Cypress Semiconductor; 3 pages; Apr. 15, 2007.

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