Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive
Reexamination Certificate
2002-08-09
2004-04-20
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Transient responsive
C361S056000
Reexamination Certificate
active
06724603
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor circuits providing electrostatic discharge (ESD) protection, and more specifically, to a distributed ESD protection scheme.
BACKGROUND OF THE INVENTION
An integrated circuit may be subject to an Electrostatic Discharge (ESD) event in the manufacturing process, during assembly and testing, or in the ultimate system application. In conventional integrated circuit (IC) ESD protection schemes, special clamp circuits are often used to shunt ESD current between the power supply rails and thereby protect internal elements from damage. A type of ESD clamp circuit, known as an active Metal Oxide Semiconductor Field Effect Transistor (MOSFET) clamp circuit, typically consists of three functional elements; a Resistor-Capacitor (RC) transient detector circuit, an intermediate buffer circuit, and a large MOSFET transistor, which serves as the primary ESD current shunting device. Active MOSFET clamp circuits may be employed in networks distributed along the IC power buses to provide robust and consistent ESD protection for multiple Input/Output (I/O) pads. Multiple embodiments of such networks are shown in U.S. Pat. No. 6,385,021 entitled “Electrostatic Discharge (ESD) Protection Circuit” and assigned to the assignee hereof.
FIG. 1
illustrates one such distributed ESD network
1000
in an IC to protect multiple I/O circuits
1030
-
1032
. While only three I/O circuits are shown in this schematic, in a typical implementation the distributed network would encompass a much larger bank of I/O circuits. I/O circuit
1032
includes an external connection pad
1050
that is coupled between the V
SS
bus
1042
and the V
DD
bus
1044
. A diode
1052
has an anode connected to the V
SS
bus
1042
and a cathode connected to the I/O pad
1050
. A diode
1053
has an anode connected to the I/O pad and a cathode connected to the V
DD
bus
1044
. In one example of ESD network
1000
, the diode
1053
is formed as a P+ active in NWELL diode and the diode
1052
is formed as a N+ active in P-substrate diode. A clamp N-channel MOSFET (NMOSFET)
1054
is connected between the V
SS
bus
1042
and the V
DD
bus
1044
. The gate of clamp NMOSFET
1054
is connected to a Trigger bus
1046
. Not shown in I/O circuit
1032
is the circuitry desired to be protected, such as for example P-channel MOSFET (PMOSFET) and N-channel (NMOSFET) output drivers, and other circuit components typically required for I/O operation. I/O circuits
1030
and
1031
, each identical to I/O circuit
1032
, are also shown in
FIG. 1. A
remote trigger circuit
1040
contains an RC transient detector circuit
1063
and a buffer circuit
1064
. RC transient detector circuit
1063
includes a capacitor
1061
connected between the V
SS
bus
1042
and a node
1065
, and a resistor
1062
connected between this same node and the V
DD
bus
1044
. Buffer circuit
1064
may, for example, contain a series of three series-connected CMOS inverter stages, not shown, between the input at node
1065
, and the output to the Trigger bus
1046
at node
1066
. Each inverter stage typically has a PMOSFET with its source connected to the V
DD
bus
1044
and a NMOSFET with its source connected to the V
SS
bus
1042
.
Three buses are shown in
FIG. 1
, a V
SS
bus
1042
, a V
DD
bus
1044
, and a Trigger bus
1046
. These buses are typically routed around all or part of the IC periphery, to serve the I/O circuits normally placed in this region. A series of incremental bus resistors, each labeled R
1
, is shown on the V
DD
bus
1044
between two adjacent I/O circuits, or an I/O circuit and an adjacent remote trigger circuit. Each resistor represents the distributed parasitic metal resistance for that segment of the V
DD
bus
1044
between two adjacent circuits. The bus length from the physical center of one such circuit to the physical center of the adjacent circuit may be used in making these resistance calculations. While these resistors are all shown with the label R
1
, it should be understood that these resistance values often vary considerably in magnitude as the physical spacing between I/O circuits, or between an I/O circuit and a remote trigger circuit, is varied. Similarly variable incremental bus resistors, each labeled R
2
, are shown on the Trigger bus
1046
. Incremental bus resistors may also be shown on the V
SS
bus
1042
, but are not included in
FIG. 1
in order to clarify the schematic. Note that in a typical IC application, additional I/O circuits and additional incremental bus resistors (R
1
, R
2
) may be added to the ESD protection network, as indicated by the dots placed to the left and right of the elements shown in FIG.
1
.
Integrated circuits are often most susceptible to damage during positive ESD events coupled onto an I/O pad referenced to grounded V
SS
. The primary response of ESD network
1000
to this event applied to I/O pad
1050
in
FIG. 1
is as follows. Diode
1053
forward biases as the I/O pad voltage very quickly ramps well above 0.7V. This then produces a rapid voltage increase over time (dV/dt), or voltage slew rate on the V
DD
bus
1044
. The RC transient detector circuit
1063
is one type of voltage transient detector circuit or voltage slew rate sensor circuit. In response to the very rapid ESD-induced dV/dt on the V
DD
Bus
1044
, transient detector circuit
1063
initially holds node
1065
well below V
DD
. The buffer circuit
1064
senses this input low and outputs an inverted and amplified signal that drives the Trigger bus
1046
to V
DD
. This turns on the multiple clamp NMOSFETs
1054
distributed in each I/O circuit. Note that since the remote trigger circuit
1040
is driving only gates of the distributed clamp NMOSFETs
1054
, the resulting current routed onto the Trigger bus
1046
is very small. Once turned on, this cumulative network of clamp NMOSFETs acts as a low resistance shunt between the V
DD
bus
1044
and the V
SS
bus
1042
. The clamp NMOSFETs will remain conductive for a period of time that is determined by the RC time constant of the transient detector circuit
1063
. This time constant should be set to exceed the typical duration of an ESD event (200-500 nanoseconds), while short enough to avoid false triggering of the clamp NMOSFETs during normal ramp up of the V
DD
bus. The V
DD
ramp up during normal IC operation typically requires 1-5 microseconds.
As described above, transient detector circuits respond to an applied ESD event by sensing a rapid voltage increase over time (dV/dt) on the V
DD
bus. It should be pointed out that another type of ESD detector circuit, a voltage threshold detector circuit, exists in the prior art. Voltage threshold detector circuits respond to an applied ESD event by sensing that a predetermined voltage threshold on the V
DD
bus has been exceeded. If this threshold is not exceeded, then the clamp NMOSFETs remain nonconductive.
During the ESD event described above, the I/O pad 1050 voltage rises to a peak level set by the sum of the voltage drops as the peak current of the applied ESD event flows through the intended dissipation paths. In the industry standard 200V Machine Model ESD event, the peak current forced through the IC may reach about 3.8A. In order to protect fragile elements in I/O circuit
1032
, the ESD clamp network must typically prevent the I/O pad 1050 voltage from rising above a critical voltage failure threshold, which typically varies in a range from 6-10V, depending on process technology and output buffer configuration. Assuming, for example, an 8.0V failure threshold for the I/O circuit and a 3.8A peak ESD current, the net resistance through the entire dissipation path may not exceed about 2.1 ohms. Such an ESD path requires large active devices and robust interconnections between these devices.
U.S. Pat. No. 6,385,021, from which
FIG. 1
is based, teaches the benefit of distributing small clamp NMOSFETs
1054
in each of the I/O circuits, as opposed to less frequent placement of larger clamp NMOSFETs along the power supply bus
Akers Matthew D
Hall Geoffrey B.
Kamat Vishnu G.
Krasin Alexander
Miller James W.
Jackson Stephen W.
King Robert L.
Kitov Zeev
Vo Kim-Marie
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