Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – With means to increase breakdown voltage
Reexamination Certificate
1999-02-01
2001-08-28
Picardat, Kevin M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
With means to increase breakdown voltage
C257S355000, C257S356000, C257S360000
Reexamination Certificate
active
06281527
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electrostatic discharge protection for semiconductor integrated circuitry. More particularly, the present invention relates to an electrostatic discharge protection circuit with a high trigger current.
2. Description of the Related Art
In sub-micron CMOS technologies, electrostatic discharge (ESD) protection has become a main concern in relation to the reliability of semiconductor integrated circuitry. Usually, MOS transistors near IC pads are designed with enlarged dimensions to provide on-chip ESD robustness. However, CMOS integrated circuits have become more vulnerable to ESD damage due to advanced processes such as the use of light-doped drains (LDDs) and clad silicide diffusions. Moreover, the fact that MOS transistors with enlarged dimensions occupy more layout area is contrary to the trend of scale miniaturization.
U.S. Pat. Nos. 5,012,317and 5,336,908disclose a lateral semiconductor-controlled rectifier (LSCR) as an on-chip ESD protection circuit. The required voltage for triggering conventional LSCR's relies heavily upon the junction breakdown between a substrate and the well region formed therein, being therefore in the range of about 30 ~50V. Thus, the conventional LSCR's may not offer effective ESD protection for sub-micron CMOS devices because the gate oxides of the MOS transistors are permanently damaged before triggering.
To reduce the trigger voltage of the LSCR's without increasing the leakage current, a modified LSCR incorporating a field oxide device has been proposed by A. Amerasekera and C. Duvvury, as disclosed in “ESD in Silicon Integrated Circuits,” John Wieley & Sons Press, 1998, p.90; furthermore, an LSCR triggered by a zener diode has been disclosed in U.S. Pat. No. 5,343,053. The trigger voltage can be further reduced to 10~15V by replacing the aforementioned field oxide device with a thin oxide MOS transistor as disclosed in U.S. Pat. No. 5,465,189. The cross-sectional view of the low voltage triggering SCR (LVTSCR) is depicted in FIG.
1
.
In
FIG. 1
, the LVTSCR is fabricated onto a P-type semiconductor substrate
10
in which an N-well
11
is provided. A P-type doped region
12
and an N-type doped region
13
are spaced apart and formed in the N-well
11
while tied together to an IC pad
1
coupled to an internal circuit
2
. The internal circuit
2
denotes the core circuit of an integrated circuit to be protected by the LVTSCR. Another N-type doped region
14
and P-type doped region
15
are spaced apart and formed in the P-type semiconductor substrate
10
while tied together to a power node V
SS
that is powered by a ground potential under normal operation.
In addition, an N-type doped region
16
is provided with one portion formed in the N-well
11
and another portion formed in the P-type semiconductor substrate
10
to span the P/N junction therebetween. A gate structure
17
is disposed on the P-type semiconductor substrate
10
between the N-type doped regions
14
and
16
. From bottom to top, the gate structure
17
comprises an oxide layer
18
formed on the P-type semiconductor substrate
10
and an electrode layer
19
connected to the power node V
SS
.
Accordingly, the P-type doped region
12
, N-well
11
and P-type semiconductor substrate
10
constitute the emitter, base, and collector of a parasitic PNP bipolar junction transistor
20
, respectively. Moreover, the P-type semiconductor substrate
10
, N-well
11
, and N-type doped region
14
constitute the collector, base, and emitter of a parasitic NPN bipolar junction transistor
21
, respectively. The equivalent circuit of
FIG. 1
is illustrated in
FIG. 2
, wherein resistors
22
5
and
23
designate the associated parasitic resistance spread over the N-well
11
and the P-type semiconductor substrate
10
. In addition, reference numeral
24
designates the MOS transistor constituted by the N-type doped regions
14
and
16
, and the gate structure
17
.
In the conventional LVTSCR, the trigger voltage is reduced, and so is the trigger current. If the LVTSCR suffers from external overshooting or undershooting noises under normal operation, it may be triggered to turn on improperly.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an electrostatic discharge protection circuit with high trigger current for preventing the LSCR from improper conduction when suffering from the external overshooting or undershooting noises under normal operation.
The present invention achieves the above-indicated object by providing an ESD protection circuit for protecting a circuit, comprising a lateral semiconductor-controlled rectifier, a MOS transistor, and a current-sinking device. The lateral semiconductor-controlled rectifier is coupled to the circuit and provided with a first common region and a second common region. The MOS transistor integrated with the lateral semiconductor-controlled rectifier includes the first common region. The current-sinking device integrated with the lateral semiconductor controlled rectifier includes the second common region.
Therefore, the current-sinking device shunts the majority of a discharge current when the MOS transistor enters breakdown, thereby increasing the trigger current of the lateral semiconductor-controlled rectifier. When external overshooting or undershooting noises occur under the normal operation, the potential at the pad can be clamped to the snapback voltage of the PNP transistor because of the high trigger current provided by the ESD protection circuit in accordance with the present invention, thus not entering PNPN conduction. Therefore, the internal circuit is immune to function disorder or device damage.
REFERENCES:
patent: 5012317 (1991-04-01), Rountre
patent: 5336908 (1994-08-01), Roberts
patent: 5343053 (1994-08-01), Avery
patent: 5465189 (1995-11-01), Polgreen et al.
Chen D. M.
Ladas & Parry
Picardat Kevin M.
Winbond Electronics Corp.
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