Electrostatic discharge protection circuit of non-gated...

Details Electrostatic discharge protection circuit of non-gated... Electrostatic discharge protection circuit of non-gated...

2006-11-28

2006-11-28

Estrada, Michelle (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Isolation by pn junction only

C257SE21352, C257SE21362

Reexamination Certificate

active

07141484

ABSTRACT:
A non-gated diode structure of a silicon-on-insulator, having a silicon-on-insulator substrate, a pair of isolating structures, a first type doped region and a second type doped region. The silicon-on-insulation substrate has a stack of a substrate, an insulation layer and a silicon layer. The isolating structures are located in the silicon layer to define a well region. The first and second type doped regions are located in the well and are adjacent to the isolating structures. Such a non-gated diode structure can be applied to an electrostatic discharge protection circuit to increase the electrostatic discharge protection voltage or current. In addition, a fabrication method of the non-gated diode is also introduced. This non-gated diode can be also fabricated in the general bulk CMOS process, and used in the on-chip ESD protection circuits.

REFERENCES:
patent: 3481801 (1969-12-01), Hugle
patent: 5122474 (1992-06-01), Harrington, III
patent: 5688722 (1997-11-01), Harrington, III
patent: 6015993 (2000-01-01), Voldman et al.
patent: 6310365 (2001-10-01), Chen
patent: 6894324 (2005-05-01), Ker et al.

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