Electrostatic discharge protection circuit having a reduced...

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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Reexamination Certificate

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08050003

ABSTRACT:
The present invention discloses an electrostatic discharge protection circuit. The electrostatic discharge protection circuit of the present invention includes a transfer unit that transfers electrostaticity from at least one of a plurality of input/output pads to a boost bus line, a trigger unit that responds to the electrostaticity transferred via the boost bus line to detect a trigger voltage and apply it to a trigger bus line, and a plurality of clamp units that are connected between the input/output pads and an internal circuit. The clamp units are triggered by the trigger voltage of the trigger unit to discharge electrostaticity of the input/output pads to a first or second power supply voltage line, thereby safely protecting the internal circuit from electrostatic damage and lowering the operating voltage of the clamp unit with minimum costs without increasing an area of the electrostatic discharge protective circuit within a semiconductor integrated circuit.

REFERENCES:
patent: 6724603 (2004-04-01), Miller et al.
patent: 7593202 (2009-09-01), Khazhinsky et al.
patent: 2004/0027742 (2004-02-01), Miller et al.
patent: 2007/0195472 (2007-08-01), Kwak et al.
patent: 2009/0323237 (2009-12-01), Kwak
patent: 0170896 (1999-03-01), None
patent: 1020050026915 (2005-03-01), None
MC Jung et al., ESD Protection Circuit with an Improved ESD Capability for Input or Output Circuit Protection, (No month) 2005 IEEE, pp. 468-471.
Michael Stockringer, et al; “Boosted and Distributed Rail Clamp Networks for ESD Protection in Advanced CMOS Technologies”, Microelectronics and Reliability vol. 45, Issue 2, Feb. 2005, pp. 211-222.

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