Electrostatic discharge protection circuit for protecting CMOS t

Details Electrostatic discharge protection circuit for protecting CMOS t Electrostatic discharge protection circuit for protecting CMOS t

1995-06-30

1998-04-28

Fleming, Fritz

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, H02H 900

Patent

active

057453233

ABSTRACT:
An apparatus and method for protecting semiconductor switching devices from damage due to electrostatic discharge is provided. The apparatus detects the occurrence of an ESD event, and turns the switching circuit to an operating state in which electrostatic charge is dissipated through the switching circuit. In embodiments of the invention, the switching circuit is a CMOS inverter circuit and the apparatus includes a PMOS transistor that upon occurrence of an ESD event couples an output of the inverter circuit to ground to discharge the electrostatic charge.

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