Electrostatic discharge protection circuit for protecting...

Details Electrostatic discharge protection circuit for protecting... Electrostatic discharge protection circuit for protecting...

2002-01-07

2003-10-28

Vu, Bao Q. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S091100, C361S111000

Reexamination Certificate

active

06639772

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. More particularly, the present invention relates to an electrostatic discharge (ESD) protection circuit for protecting input and output buffers.
2. Description of Related Art
In the process of manufacturing an integrated circuit (IC) such as a dynamic random access memory (DRAM) and a static random access memory (SRAM) or after complete fabrication of a silicon chip, electrostatic discharge (ESD) events are one of the principle reasons for IC failures. For example, somebody walking on a carpet in high relative humidity (RH) may generate several hundred to several thousand volts of static electricity. When the relative humidity of the surrounding air is low, over ten thousand volts of static electricity may be generated. In addition, some sealed machine IC package or instruments for monitoring IC chips may produce several hundred to several thousand volts of static electricity depending on weather and humidity factors.
As soon as a charged body contacts a silicon chip, charges may discharge towards the chip leading to possible circuit breakdown and IC failure. To prevent any damage to the IC caused by an ESD, various ESD protection methods have been developed.
FIG. 1
is a circuit diagram of a conventional ESD protection circuit. As shown in
FIG. 1
, the drain terminal of a PMOS transistor
102
is coupled to an input pad
106
. The gate terminal, the source terminal and the substrate terminal of the PMOS transistor
102
are connected to a voltage source VDD. The drain terminal of an NMOS transistor
104
is coupled to an output pad
106
. The gate terminal, the source terminal and the substrate terminal are connected to a voltage source VSS.
In a normal operating mode, the input pad is free of any electrostatic discharge. Since the gate terminal of the PMOS transistor
102
is coupled to the voltage source VDD and the gate terminal of the NMOS transistor
104
is coupled to the voltage source VSS, the PMOS transistor
102
and the NMOS transistor
104
are both in the cut off state. Hence, no leakage current flows from the PMOS transistor
102
and the NMOS transistor
104
.
In the PS mode (a positive voltage pulse is applied to the input pad
106
with the source terminal VSS connected to ground), an electrostatic discharge in the form of a positive voltage pulse is applied to the input pad
106
. The positive voltage pulse is transmitted to the drain terminal of the NMOS transistor
104
. Moreover, the voltage source VSS terminal can be regarded as the ground connected during the ESD transient. Hence, once the positive voltage pulse exceeds the avalanche breakdown voltage of the drain and the substrate terminal of the NMOS transistor
104
, the junction between the drain terminal and the substrate terminal breaks down. Ultimately, the drain terminal and the substrate terminal of the NMOS transistor
104
form an ESD bypass preventing the overloading of devices including the input buffer
108
and the internal circuit
110
.
In the NS mode (a negative voltage pulse is applied to the input pad
106
with the voltage source VSS connected to ground), an electrostatic discharge in the form of a negative voltage pulse is applied to the input pad
106
. The substrate terminal and the drain terminal of the NMOS transistor
104
form a parasitic diode (not shown). Moreover, voltage source VSS terminal can be regarded as connected to the ground during ESD transient. Hence, the parasitic diode (not shown) within the NMOS transistor
104
forms a forward bias bypass channeling away the current due to the passage of a negative voltage pulse through the input pad
106
. With the parasitic diode (not shown) within the NMOS transistor
104
serving as a bypass, current surge produced by the ESD is prevented from overloading the input buffer
108
and the internal circuit
110
.
In the PD mode (a positive voltage pulse is applied to the input pad
106
with the voltage source VDD connected to ground), an electrostatic discharge in the form of a positive voltage pulse is applied to the input pad
106
. The substrate terminal and the drain terminal of the PMOS transistor
102
form a parasitic diode (not shown). Moreover, the voltage source VDD terminal can be regarded as connected to the ground during ESD transient. Hence, the parasitic diode (not shown) within the PMOS transistor
102
forms a forward bias bypass channeling away the current due to the passage of a positive voltage pulse through the input pad
106
. With the parasitic diode (not shown) within the PMOS transistor
102
serving as a bypass, current surge produced by the ESD is prevented from overloading the input buffer
108
and the internal circuit
110
.
In the ND mode (a negative voltage pulse is applied to the input pad
106
with the source terminal VDD connected to ground), an electrostatic discharge in the form of a negative voltage pulse is applied to the input pad
106
. The negative voltage pulse is transmitted to the drain terminal of the PMOS transistor
102
. Moreover, the voltage source VDD terminal can be regarded as the ground connected during the ESD transient. Hence, once the negative voltage pulse exceeds the avalanche breakdown voltage of the drain and the substrate terminal of the PMOS transistor
102
, the junction between the drain terminal and the substrate terminal breaks down. Ultimately, the drain terminal and the substrate terminal of the PMOS transistor
102
form an ESD bypass preventing the overloading of the input buffer
108
and the internal circuit
110
.
In
FIG. 1
, if the input buffer is changed to an output buffer and the input pad
106
is changed to an output pad, the circuit is immediately transformed into an electrostatic discharge protection circuit for protecting an output buffer.
However, following the miniaturization of semiconductor devices, thickness of the gate oxide layer within the PMOS transistor
112
and the NMOS transistor
114
of the input buffer
108
must be reduced. Hence, the avalanche breakdown voltage of the gate oxide layer is reduced correspondingly. If the avalanche breakdown voltage of the gate oxide layer for the PMOS transistor
112
and the NMOS transistor
114
approaches the cumulative junction breakdown voltage between the PMOS transistor
102
and the NMOS transistor
104
, the high voltage discharge may punch through the gate oxide layer of both the PMOS transistor
112
and the NMOS transistor
114
. Thus, the PMOS transistor
112
and the NMOS transistor
114
may be severely damaged.
In addition, the PMOS transistor
102
and the NMOS transistor
104
that serve as a bypass for ESD have a multi-finger MOS layout. In general, a multi-finger MOS layout has non-uniform conductance so that ESD current rarely flows through each MOS uniformly.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide an electrostatic discharge (ESD) protection circuit for protecting input and output buffers. Through the application of a voltage to the substrate and gate terminal of a metallic-oxide-semiconductor (MOS) transistor used especially for bypassing ESD, the cumulative junction breakdown voltage of the MOS transistor is reduced and non-uniform conductance due to a multi-finger MOS layout design is improved. Consequently, damages to the input buffer, the output buffer and other internal circuits resulting from an ESD are minimized.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an ESD protection circuit for protecting input and output buffers. A first voltage source and a second voltage source are provided to the ESD protection circuit. The ESD protection circuit is coupled to a bonding pad. The ESD circuit comprises a first resistor, a first PMOS transistor, a first NMOS transistor, a first diode series, a second PMOS transistor, a second resistor, a third PMOS transistor, a second NMOS tr

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