Electrostatic discharge protection circuit for integrated circui

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

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Details

361 91, 361118, H01L 2906

Patent

active

054521718

ABSTRACT:
An ESD protection circuit that uses the well-known SCR latchup effect present in CMOS processes to divert the ESD current pulse away from sensitive circuit structures. The circuit uses an inverter trigger device, with a voltage divider on its output, to control the amount of voltage necessary to cause latchup. This feature enables the SCR to absorb a high current pulse on the CMOS pad structures caused by an ESD event, while also preventing the circuit from latching when an ordinary CMOS voltage is applied to the pad while the circuit being protected is unpowered. The circuit insures that the SCR will latch independent of breakdown effects, while also allowing the threshold voltage at which latchup occurs to be adjusted into the circuit by varying the sizes of two FETS used as the voltage divider.

REFERENCES:
patent: 5077591 (1991-12-01), Chen et al.

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