Electrostatic discharge protection circuit and transistor

Details Electrostatic discharge protection circuit and transistor Electrostatic discharge protection circuit and transistor

1999-04-09

2001-06-19

Meier, Stephen D. (Department: 2822)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Forming lateral transistor structure

C438S312000, C438S337000, C438S350000, C438S524000

Reexamination Certificate

active

06248639

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to protecting semiconductor circuits against electrostatic discharge, and more particularly, to a protection circuit having a transistor used for protecting semiconductor circuits against electrostatic discharge.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuits are prone to electrostatic breakdown by static electricity charged on the human body or other similar sources. Such electrostatic discharge (ESD) causes breakdown of the PN junction surface and breakdown of various films and layers formed on the device such as oxide films.
Various techniques have been devised for protecting circuits against damage caused by electrostatic discharge, such as those generated from the human body. These circuits have become very important because the slightest handling by an individual during semiconductor processing or in a final product could create enough electrostatic discharge to break down an oxide film or PN junction, thus ruining the semiconductor device.
Some ESD protection devices and circuits use a combination of diodes and resistors to protect the semiconductor circuits. Other ESD protection circuits use various types of transistors, such as disclosed in U.S. Pat. No. 4,989,057 to Lu, which discloses a floating body field effect transistor having a defined breakdown voltage, and a lower holding voltage to serve as a clamp for electrostatic discharge voltages, minimizing thermal power dissipation within the semiconductor layer.
U.S. Pat. No. 5,623,387 to Li, et al., uses a split bipolar transistor with the transistor layout exhibiting very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents current hogging, causing an ESD failure. The transistor uses the snap-back effect to increase current carrying capacity. The transistor layout has metal contacts that are positioned away from regions of high energy dissipation. The use of high-diffusing phosphorous in various N-type doped regions prevents sharp changes in electron density.
Other circuits do not use as many contacts and doped regions, but make use of a transistor with the emitter and base shorted to show a bistable behavior having a high impedance in the avalanche breakdown region and a low impedance in the bipolar snap-back region.
In such transistor devices, it is desirable to increase the clamping efficiency (i.e., limiting the voltage at a point in a circuit) by limiting the maximum voltage developed at the collector terminal. It is also desirable to have the smallest snap-back voltage to increase the device failure threshold during electrostatic discharge conditions.
These two requirements are typically mutually exclusive because a low collector-to-base breakdown voltage requires a generally low base dopant level, while a low clamping voltage during snap-back operation requires a high current gain and a generally high base dopant level.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a circuit for protecting against electrostatic discharge by increasing the clamping efficiency of protection and reducing the snap-back voltage.
It is also an object of the present invention to provide a transistor used in a circuit for protecting against electrostatic discharge that achieves a low collector-to-base breakdown voltage and a low clamping voltage during snap-back operation.
The circuit of the present invention now protects against electrostatic discharge by using a transistor having a base with two doped regions giving a unique configuration so that one doped region achieves a low collector-to-base breakdown voltage and the other doped region achieves a low snap-back voltage. The circuit includes a pad, which receives a signal from an external signal source, such as a power source or other signal. A semiconductor body of a first conductivity type serves as the collector of the transistor and is connected to the pad. A first doped region of a second conductivity type is contained in the semiconductor body and serves as the base of the transistor and forms a collector-to-base junction with the semiconductor body. A second doped region of the first conductivity type is contained in the first doped region and serves as the emitter of the transistor and forms a base-to-emitter junction with the first doped region.
Connection means electrically connects the first and second doped regions and establishes a circuit connection between the base and emitter. The first doped region serving as the base further comprises a generally H-shaped region and a generally ring-shaped doped region forming an opening in which the second doped region serving as the emitter is received. The H-shaped doped region has a deeper junction depth than the ring-shaped doped region and a dopant concentration that is less than the dopant concentration of the ring-shaped doped region so that the H-shaped doped region achieves a low collector-to-base breakdown voltage and the ring-shaped doped region achieves a low snap-back voltage.
In one aspect of the present invention, the H-shaped doped region further comprises means for receiving and substantially encircling the ring-shaped doped region. The receiving means defines a ring-shaped recess that receives the ring-shaped doped region. The H-shaped doped region further comprises an inward formed medial section that exposes a portion of said ring-shaped doped region to the semiconductor body serving as a collector. The opening in the ring-shaped doped region exposes a portion of the H-shaped doped region to the second doped region of first conductivity serving as the emitter. The H-shaped doped region further comprises a central slot and includes a doped region of second conductivity received in the central slot and engaging the shorted connection means.
In still another aspect of the present invention, the shorted connection means comprises a contact engaging both first and second doped regions serving as the base and emitter. The shorted connection means can also include a ground connection. The semiconductor body serving as the collector of the transistor further comprises an epitaxial layer. The semiconductor body also further comprises a sink for electrons.
In still another aspect of the present invention, the semiconductor body of the first conductivity type comprises an N-type material, and the doped region of second conductivity type comprises a P-type material.
In a method aspect of the invention, a transistor is formed for protecting against electrostatic discharge. A semiconductor body of a first conductivity is formed to serve as the collector of the transistor. A first doped region of a second conductivity is then formed in the semiconductor body to serve as the base of the transistor and form a collector-to-base junction with semiconductor body. A second doped region of the first conductivity type is formed in the first doped region to serve as the emitter of the transistor and form a base-to-emitter junction with the first doped region and second conductivity type.
The first doped region is further formed by forming a generally H-shaped doped region and then forming a generally ring-shaped doped region and forming an opening in which the second doped region serving as the emitter is received. This H-shaped doped region is formed with a deeper junction surface than said ring-shaped doped region and a dopant concentration that is less than the dopant concentration of the ring-shaped doped region so that when the first and second doped regions are connected, the H-shaped doped region achieves a low collector-to-base breakdown voltage, and the ring-shaped doped region achieves a low snap-back voltage when the transistor is placed in the circuit subject to electrostatic discharge.


REFERENCES:
patent: 4735912 (1988-04-01), Kawakatsu
patent: 4989057 (1991-01-01), Lu
patent: 4994874 (1991-02-01), Shimizu et al.
patent: 5181092 (1993-01-01), Atsumi
patent: 5304839 (1994-04-01), Chen et al.
patent: 5369298 (1994-11-01), Honda et al.
patent: 5371395 (1994-12-01)

Affiliated with

Also associated with

Rating

Electrostatic discharge protection circuit and transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrostatic discharge protection circuit and transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrostatic discharge protection circuit and transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2452562